top_fmdm_project.pcf

ISE7.1

        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_scnt_cmp_q"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe0"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe1"
        BEL "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig0"
        BEL "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig1"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1170.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1174.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1178.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1182.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1186.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1190.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1194.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1198.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1202.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1206.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1210.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1214.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1218.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1222.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1226.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1230.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1234.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1238.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1242.B_pins<53>"
        PIN
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1246.B_pins<53>";
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1170.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1170.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1174.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1174.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1178.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1178.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1182.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1182.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1186.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1186.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1190.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1190.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1194.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1194.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1198.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1198.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1202.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1202.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1206.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1206.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1210.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1210.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1214.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1214.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1218.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1218.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1222.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1222.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1226.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1226.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1230.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1230.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1234.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1234.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1238.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1238.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1242.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1242.A"
        PINNAME CLKA;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1246.A_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1246.A"
        PINNAME CLKA;
TIMEGRP J_CLK = BEL "U_icon_pro/icon_pro/u_icon/u_tdi_reg" BEL
        "U_icon_pro/icon_pro/u_icon/u_tdo_reg" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/15/i_eq0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/14/i_ne0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/13/i_ne0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/12/i_ne0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/11/i_ne0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/10/i_ne0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/9/i_ne0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/8/i_ne0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/7/i_ne0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_cmd/g_target/6/i_ne0/u_target" BEL
        "U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/6/i_eq0/u_fdr" BEL
        "U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/5/i_ne0/u_fdr" BEL
        "U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/4/i_ne0/u_fdr" BEL
        "U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/3/i_ne0/u_fdr" BEL
        "U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/2/i_ne0/u_fdr" BEL
        "U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/1/i_ne0/u_fdr" BEL
        "U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/0/i_ne0/u_fdr" BEL
        "U_icon_pro/icon_pro/u_icon/u_sync/u_sync" BEL
        "U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/5/u_fdre" BEL
        "U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/4/u_fdre" BEL
        "U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/3/u_fdre" BEL
        "U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/2/u_fdre" BEL
        "U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/1/u_fdre" BEL
        "U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/0/u_fdre" BEL
        "U_icon_pro/icon_pro/u_icon/u_stat/u_tdo" BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_rst/u_halt_xfer/u_tfdre" BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_rst/u_arm_xfer/u_tfdre" BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_nmu_eq1/u_idout/i_srl_t2/u_srlc16e"
        BEL
        "U_ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/idout.SLICE_FMC15_BLACKBOX"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_nmu_eq1/u_idout/i_srl_t2/u_srlc16e"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/s0_cfg/i_srl_t2/u_srlc16e"
        BEL
        "U_ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_14.SLICE_GMC15_BLACKBOX"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/1/si_cfg/i_srl_t2/u_srlc16e"
        BEL
        "U_ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_14.SLICE_FMC15_BLACKBOX"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/2/si_cfg/i_srl_t2/u_srlc16e"
        BEL
        "U_ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_13.SLICE_GMC15_BLACKBOX"
        BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/3/si_cfg/i_srl_t2/u_srlc16e"
        BEL
        "U_ila_pro_0/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_11.SLICE_GMC15_BLACKBOX"
        BEL