top_fmdm_project.pcf

ISE7.1

//! **************************************************************************
// Written by: Map H.42 on Tue Jul 24 10:27:08 2007
//! **************************************************************************

SCHEMATIC START;
COMP "adc_wide<0>" LOCATE = SITE "D21" LEVEL 1;
COMP "adc_wide<1>" LOCATE = SITE "E22" LEVEL 1;
COMP "max3232_rec_fpga" LOCATE = SITE "L2" LEVEL 1;
COMP "adc_wide<2>" LOCATE = SITE "E21" LEVEL 1;
COMP "adc_wide<3>" LOCATE = SITE "H19" LEVEL 1;
COMP "adc_wide<4>" LOCATE = SITE "H20" LEVEL 1;
COMP "adc_wide<5>" LOCATE = SITE "G22" LEVEL 1;
COMP "adc_wide<6>" LOCATE = SITE "G21" LEVEL 1;
COMP "adc_wide<7>" LOCATE = SITE "H22" LEVEL 1;
COMP "adc_wide<8>" LOCATE = SITE "H21" LEVEL 1;
COMP "adc1_clk" LOCATE = SITE "D22" LEVEL 1;
COMP "adc_wide<9>" LOCATE = SITE "K22" LEVEL 1;
COMP "adc2_clk" LOCATE = SITE "AA20" LEVEL 1;
COMP "delay_in<0>" LOCATE = SITE "G1" LEVEL 1;
COMP "delay_in<1>" LOCATE = SITE "A10" LEVEL 1;
COMP "adc_wide<10>" LOCATE = SITE "K21" LEVEL 1;
COMP "delay_in<2>" LOCATE = SITE "D2" LEVEL 1;
COMP "adc_wide<11>" LOCATE = SITE "L22" LEVEL 1;
COMP "delay_in<3>" LOCATE = SITE "A6" LEVEL 1;
COMP "delay_in<4>" LOCATE = SITE "E1" LEVEL 1;
COMP "delay_in<5>" LOCATE = SITE "B6" LEVEL 1;
COMP "delay_in<6>" LOCATE = SITE "E2" LEVEL 1;
COMP "delay_in<7>" LOCATE = SITE "A4" LEVEL 1;
COMP "delay_in<8>" LOCATE = SITE "E3" LEVEL 1;
COMP "delay_in<9>" LOCATE = SITE "B4" LEVEL 1;
COMP "delay_in<10>" LOCATE = SITE "D1" LEVEL 1;
COMP "delay_in<11>" LOCATE = SITE "E4" LEVEL 1;
COMP "delay_in<12>" LOCATE = SITE "K1" LEVEL 1;
COMP "delay_in<20>" LOCATE = SITE "H4" LEVEL 1;
COMP "delay_in<13>" LOCATE = SITE "G2" LEVEL 1;
COMP "delay_in<14>" LOCATE = SITE "K2" LEVEL 1;
COMP "delay_in<15>" LOCATE = SITE "H1" LEVEL 1;
COMP "delay_in<16>" LOCATE = SITE "K3" LEVEL 1;
COMP "delay_in<17>" LOCATE = SITE "H2" LEVEL 1;
COMP "delay_in<18>" LOCATE = SITE "K4" LEVEL 1;
COMP "delay_in<19>" LOCATE = SITE "H3" LEVEL 1;
COMP "adc_log<10>" LOCATE = SITE "AA10" LEVEL 1;
COMP "adc_log<11>" LOCATE = SITE "AB5" LEVEL 1;
COMP "adc_narrow<10>" LOCATE = SITE "C22" LEVEL 1;
COMP "adc_narrow<11>" LOCATE = SITE "C21" LEVEL 1;
COMP "test1" LOCATE = SITE "R2" LEVEL 1;
COMP "test3" LOCATE = SITE "AB9" LEVEL 1;
COMP "reset" LOCATE = SITE "A15" LEVEL 1;
COMP "test2<0>" LOCATE = SITE "P22" LEVEL 1;
COMP "test2<1>" LOCATE = SITE "P21" LEVEL 1;
COMP "test2<2>" LOCATE = SITE "P20" LEVEL 1;
COMP "test2<3>" LOCATE = SITE "P19" LEVEL 1;
COMP "test2<4>" LOCATE = SITE "R20" LEVEL 1;
COMP "test2<5>" LOCATE = SITE "R19" LEVEL 1;
COMP "test2<6>" LOCATE = SITE "AB15" LEVEL 1;
COMP "test2<7>" LOCATE = SITE "AA15" LEVEL 1;
COMP "max3232_tr_fpga" LOCATE = SITE "L3" LEVEL 1;
COMP "adc_log<0>" LOCATE = SITE "AB18" LEVEL 1;
COMP "adc_log<1>" LOCATE = SITE "AA18" LEVEL 1;
COMP "adc_log<2>" LOCATE = SITE "AB17" LEVEL 1;
COMP "adc_narrow<0>" LOCATE = SITE "B10" LEVEL 1;
COMP "adc_log<3>" LOCATE = SITE "AA17" LEVEL 1;
COMP "adc_narrow<1>" LOCATE = SITE "A11" LEVEL 1;
COMP "adc_log<4>" LOCATE = SITE "AB13" LEVEL 1;
COMP "adc_narrow<2>" LOCATE = SITE "B11" LEVEL 1;
COMP "adc_log<5>" LOCATE = SITE "AA13" LEVEL 1;
COMP "adc_narrow<3>" LOCATE = SITE "B12" LEVEL 1;
COMP "adc_log<6>" LOCATE = SITE "AB12" LEVEL 1;
COMP "adc_narrow<4>" LOCATE = SITE "A13" LEVEL 1;
COMP "adc_log<7>" LOCATE = SITE "AA12" LEVEL 1;
COMP "adc_narrow<5>" LOCATE = SITE "B13" LEVEL 1;
COMP "adc_log<8>" LOCATE = SITE "AA11" LEVEL 1;
COMP "adc_narrow<6>" LOCATE = SITE "A17" LEVEL 1;
COMP "adc_log<9>" LOCATE = SITE "AB10" LEVEL 1;
COMP "adc_narrow<7>" LOCATE = SITE "B17" LEVEL 1;
COMP "adc_narrow<8>" LOCATE = SITE "A19" LEVEL 1;
COMP "adc_narrow<9>" LOCATE = SITE "B19" LEVEL 1;
COMP "clk20mhz" LOCATE = SITE "F13" LEVEL 1;
COMP "fmdm_select" LOCATE = SITE "C4" LEVEL 1;
NET "clk20mhz_BUFGP/IBUFG" BEL "clk20mhz_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
PIN fifo/B8.B_pins<53> = BEL "fifo/B8.B" PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1170.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1170.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1174.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1174.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1178.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1178.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1182.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1182.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1186.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1186.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1190.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1190.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1194.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1194.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1198.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1198.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1202.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1202.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1206.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1206.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1210.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1210.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1214.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1214.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1218.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1218.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1222.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1222.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1226.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1226.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1230.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1230.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1234.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1234.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1238.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1238.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1242.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1242.B"
        PINNAME CLKB;
PIN
        U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1246.B_pins<53>
        = BEL
        "U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1246.B"
        PINNAME CLKB;
TIMEGRP D_CLK = BEL "fifo_rs232_ctr/state_FFd1" PIN "fifo/B8.B_pins<53>" BEL
        "fifo/BU34" BEL "fifo/BU40" BEL "fifo/BU46" BEL "fifo/BU52" BEL
        "fifo/BU58" BEL "fifo/BU63" BEL "fifo/BU72" BEL "fifo/BU79" BEL
        "fifo/BU86" BEL "fifo/BU93" BEL "fifo/BU100" BEL "fifo/BU107" BEL
        "fifo/BU114" BEL "fifo/BU115" BEL "fifo/BU119" BEL "fifo/BU120" BEL
        "fifo/BU121" BEL "fifo/BU125" BEL "fifo/BU129" BEL "fifo/BU130" BEL
        "fifo/BU134" BEL "fifo/BU135" BEL "fifo/BU139" BEL "fifo/BU143" BEL
        "fifo/BU149" BEL "fifo/BU253" BEL "fifo/BU255" BEL "fifo/BU257" BEL
        "fifo/BU259" BEL "fifo/BU261" BEL "fifo/BU263" BEL "fifo/BU268" BEL
        "fifo/BU273" BEL "fifo/BU283" BEL "fifo/BU288" BEL "fifo/BU293" BEL
        "fifo/BU297" BEL "fifo_rs232_ctr/fifo_enable" BEL
        "fifo_rs232_ctr/state_FFd2" BEL "mux_tripple/command_7" BEL
        "mux_tripple/command_5" BEL "mux_tripple/command_6" BEL
        "uart/u_reciever/rcnt_10" BEL "uart/u_reciever/rcnt_9" BEL
        "uart/u_reciever/rcnt_8" BEL "uart/u_reciever/rcnt_7" BEL
        "uart/u_reciever/rcnt_6" BEL "uart/u_reciever/rcnt_5" BEL
        "uart/u_reciever/rcnt_4" BEL "uart/u_reciever/rcnt_3" BEL
        "uart/u_reciever/rcnt_19" BEL "uart/u_reciever/rcnt_18" BEL
        "uart/u_reciever/rcnt_17" BEL "uart/u_reciever/rcnt_16" BEL
        "uart/u_reciever/rcnt_15" BEL "uart/u_reciever/rcnt_11" BEL
        "uart/u_reciever/rcnt_14" BEL "uart/u_reciever/rcnt_13" BEL
        "uart/u_reciever/rcnt_12" BEL "uart/u_reciever/rbufs_5" BEL
        "uart/u_reciever/rbufs_6" BEL "uart/u_reciever/rbufs_7" BEL
        "uart/u_reciever/rbuf_7" BEL "uart/u_reciever/count_3" BEL
        "uart/u_reciever/rcnt_31" BEL "uart/u_reciever/r_ready" BEL
        "uart/u_reciever/rbufs_0" BEL "uart/u_reciever/rbufs_1" BEL
        "uart/u_reciever/rbufs_2" BEL "uart/u_reciever/rbufs_3" BEL
        "uart/u_reciever/rbufs_4" BEL "uart/u_reciever/rbuf_0" BEL
        "uart/u_reciever/rbuf_1" BEL "uart/u_reciever/rbuf_2" BEL
        "uart/u_reciever/rbuf_3" BEL "uart/u_reciever/rbuf_4" BEL