reciever.vhd

ISE7.1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity reciever is
generic(framlenr:integer:=8);
port(
bclkr,resetr,rxdr:in std_logic;	                       --定义输入输出信号
r_ready:out std_logic;
rbuf:out std_logic_vector(7 downto 0));
end reciever;

architecture Behavioral of reciever is
type states is(r_start,r_center,r_wait,r_sample,r_stop);		   --定义各子态
signal state:states:=r_start;
signal rxd_sync:std_logic;
begin
--pro1:process(rxdr)
--begin 
--     if rxdr='0' then rxd_sync<='0';
--	  else rxd_sync<='1';
--	  end if;
--end process;
rxd_sync<=rxdr;

pro2:process(bclkr,resetr,rxd_sync)								 	    --主控时序、组合进程
variable count:std_logic_vector(3 downto 0);
variable rcnt:integer:=0;												    --定义中间变量
variable rbufs:std_logic_vector(7 downto 0);
begin
	     if resetr='0' then 
		     count:="0000";
			  rbuf<=(others=>'0');
			  rbufs:="00000000";
			  rcnt:=0;
			  r_ready<='0';
			  state<=r_start;
			  				  --复位
		  elsif rising_edge(bclkr)then
			     case state is														  
				     when r_start=>													  --状态1，等待起始位
					                r_ready<='0';
										 if rxd_sync='0'then 
											 rcnt:=0;
											 state<=r_center;
										 else
											 state<=r_start;
										 end if;
					  when r_center=>													  --状态2，求出每位的中点
					                if rxd_sync='0' then
										     if count="0100"then 
												  count:="0000";
												  state<=r_wait;
											  else 
												  count:=count+1;
												  state<=r_center;
											  end if;
										 else 
										     state<=r_start;
										 end if;											 --状态3，等待状态
					  when r_wait=>													  
					                if count>="1110" then
										     if rcnt=framlenr then 
											    state<=r_stop;
											  else 
											    state<=r_sample;
											  end if;
										       count:="0000";
										 else 
											 count:=count+1;
											 state<=r_wait;
										 end if;
		           when r_sample=>										    	 --状态4，数据位采样检测
					                 rbufs(rcnt):=rxd_sync;		 
					                 rcnt:=rcnt+1;
										  state<=r_wait;                                                        
					  when r_stop=> 
					                r_ready<='1';
					                rbuf<=rbufs;					  --状态5,输出数据
										 state<=r_start;
					  when others=>
					                state<=r_start;
				  end case;
			end if;
end process;
end Behavioral;