accumulator_ctr_dataadjust.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:    17:20:21 01/22/07
-- Design Name:    
-- Module Name:    accumulator_ctr_dataadjust - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:  控制累加器何时发送数据，何时清零的进程
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity accumulator_ctr_dataadjust is
port(
     clk                     :in std_logic;-------adc的时钟，即select_clk选择的时钟
	  accumulator_send_clk    :out std_logic;---数据调整,选择发送log,wide,narrow脉冲.
     accumulator_clr_clk     :out std_logic											
												  ---的时钟是一致的。 -----类似发送使能。
	 );											
end accumulator_ctr_dataadjust;			

architecture Behavioral of accumulator_ctr_dataadjust is
signal clk_reverse                    :std_logic;
signal accumulator_send_clk_counter   :std_logic_vector(9 downto 0):="0000000000";
signal accumulator_clr_clk_counter    :std_logic_vector(9 downto 0):="0000000000";
begin
clr:process(clk)
	begin
			 if(rising_edge(clk))then
			    if (accumulator_send_clk_counter>="1111111111")then
				    accumulator_send_clk<='1';
					 accumulator_send_clk_counter<="0000000000";
			    else
				   accumulator_send_clk<='0';
					accumulator_send_clk_counter<=accumulator_send_clk_counter+'1';
				 end if;
			end if;
	end  process;
clk_reverse<=not clk;
enableout_accumulator:process(clk_reverse)		 -------这个进程是产生清零脉冲的。
	begin
		 if(rising_edge(clk_reverse))then
		    if (accumulator_clr_clk_counter>="1111111111")then
			   accumulator_clr_clk<='1';
				accumulator_clr_clk_counter<="0000000000";
		    else
			  accumulator_clr_clk<='0';
			  accumulator_clr_clk_counter<=accumulator_clr_clk_counter+'1';
			 end if;
		end if;
	end  process;
end Behavioral;