adc_control.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:    23:14:23 01/30/07
-- Design Name:    
-- Module Name:    adc_control - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adc_control is
 Port (   
          data_in                   :in std_logic_vector(11 downto 0):="000000000000";     ---ADC输入
          data_out_toaccumulator    :out std_logic_vector(11 downto 0);                    ----ADC输出至至加法器
          clk                       :in std_logic;                                         -----ADC输入时钟  与串口中selected_delay对应
			 reset                     :in std_logic                                          ---系统复位
		);
end adc_control;

architecture Behavioral of adc_control is
--signal data_in_buffer1:	std_logic_vector(11 downto 0);
--signal data_in_buffer2:	std_logic_vector(11 downto 0);
--begin
--	log_adcontrol:process(clk,reset)
--	begin
--	if(rising_edge(clk))then
--	 if(reset='0')then
--    data_out_toaccumulator<=(others=>'0');
--	 data_in_buffer1<=(others=>'0');
--	 data_in_buffer2<=(others=>'0');
--	 else
--	         data_in_buffer1<=data_in;	 ------------必须打两次才能消除亚稳态 尤其是高频的时候
--				data_in_buffer2<=data_in_buffer1;----------------------------------
--				data_out_toaccumulator<=data_in-"100000000000";
--    end if;
--   end if;
--end process;


begin
process(clk,reset,data_in)
	begin
	  if(reset='0')then
	      data_out_toaccumulator<=(others=>'0');
	  elsif(rising_edge(clk))then
	      data_out_toaccumulator<=data_in-"100000000000";
	  end if;
	end process;
end Behavioral;