fifo_rs232.xco

ISE7.1

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = F:\vhdlproject\0705
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = F:\vhdlproject\0705
SET device = xc2v500
# SET projectname = F:\vhdlproject\0705
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = fg456
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Asynchronous_FIFO family Xilinx,_Inc. 6.1
# END Select
# BEGIN Parameters
CSET create_rpm=false
CSET read_acknowledge=false
CSET almost_empty_flag=false
CSET write_acknowledge=false
CSET memory_type=block
CSET read_acknowledge_sense=active_high
CSET read_count_width=2
CSET fifo_depth=63
CSET component_name=fifo_rs232
CSET write_count_width=2
CSET write_count=false
CSET read_count=false
CSET write_error=false
CSET read_error=false
CSET read_error_sense=active_high
CSET almost_full_flag=false
CSET write_acknowledge_sense=active_high
CSET write_error_sense=active_high
CSET input_data_width=8
# END Parameters
GENERATE