📄 readfifo_rs232.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:58:20 01/21/07
-- Design Name:
-- Module Name: readfifo_RS232 - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description: 用来控制串口发送命令的。
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity readfifo_RS232 is
port(
reset :in std_logic;
rs232_clk_read :in std_logic; -----采样EMPTY的时钟 可以用bclk。
txd_done :in std_logic;
fifo_empty :in std_logic;------根据FIFO的空标志,只要非空则可以读,即发送串口发送命令
fifo_enable :out std_logic;
trans_com :out std_logic-----串口发送命令
) ;
end readfifo_RS232;
architecture Behavioral of readfifo_RS232 is
type states is(idle,rd_en_trcom_generate,cmd_cancel);
signal state:states:=idle;
begin
process(reset,rs232_clk_read,fifo_empty)
begin
if reset='0'then
state<=idle;
fifo_enable<='0';
trans_com<='0';
elsif rising_edge(rs232_clk_read)then
case state is
when idle=>
fifo_enable<='0';
trans_com<='0';
if fifo_empty='0' then
state<=rd_en_trcom_generate;
else
state<=idle;
end if;
when rd_en_trcom_generate=>
fifo_enable<='1';
trans_com<='1';
state<=cmd_cancel;
when cmd_cancel=>
fifo_enable<='0';
trans_com<='0';
if txd_done='1'then
if fifo_empty='1'then
state<=idle;
else
state<=rd_en_trcom_generate;
end if;
else
state<=cmd_cancel;
end if;
end case;
end if;
end process;
end Behavioral;
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