top_fmdm_project.twr

ISE7.1

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise f:\vhdlproject\vhdl0716\0716.ise -intstyle ise
-e 3 -l 3 -s 4 -xml top_fmdm_project top_fmdm_project.ncd -o
top_fmdm_project.twr top_fmdm_project.pcf


Design file:              top_fmdm_project.ncd
Physical constraint file: top_fmdm_project.pcf
Device,speed:             xc2v500,-4 (PRODUCTION 1.121 2005-07-22, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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WARNING:Timing:2666 - Constraint ignored: PATH "TS_U_TO_D_path" TIG;
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.

================================================================================
Timing constraint: TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" TO TIMEGRP "J_CLK" 30 ns;

 2931 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is  10.456ns.
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================================================================================
Timing constraint: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 ns;

 18 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.683ns.
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================================================================================
Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns;

 1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.820ns.
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================================================================================
Timing constraint: PATH "TS_U_TO_D_path" TIG;

 0 items analyzed, 0 timing errors detected.
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================================================================================
Timing constraint: PATH "TS_J_TO_D_path" TIG;

 155 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
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================================================================================
Timing constraint: PATH "TS_D_TO_J_path" TIG;

 251 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
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All constraints were met.


Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 3356 paths, 0 nets, and 1378 connections

Design statistics:
   Minimum period:  10.456ns (Maximum frequency:  95.639MHz)
   Maximum path delay from/to any node:  10.456ns


Analysis completed Tue Jul 24 10:27:35 2007
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Peak Memory Usage: 96 MB