📄 ham_code_rt.v
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`timescale 1ns/1ns
module Ham_Code_RT();
//input signal
reg clk,rst;
reg req;
reg [3:0] datain;
reg [2:0] cin;
//output signal
wire [3:0] dataout;
wire ack;
//**********************************************************
// 1111 f 1110 => e
// 1110 e 1110 => f
// 1101 d 1100 => c
// 1100 c 1101 => d
// 1011 b 1010 => a
// 1010 a 1011 => b
// 1001 9 1000 => 8
// 1000 8 1001 => 9
// 0111 7 0110 => 7
// 0110 6 0111 => 6
// 0101 5 0100 => 4
// 0100 4 0101 => 5
// 0011 3 0010 => 2
// 0010 2 0011 => 3
// 0001 1 0000 => 0
// 0000 0 0001 => 1
//*************************************************************
initial
begin
#10 clk <= 0;
rst <= 0;
req <= 0;
#100 rst <= 1;
#200 req <= 1'b1;
datain <= 4'he;//f
cin <= 3'h7;//7
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'hf;//e
cin <= 3'h0;//0
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'hc;//d
cin <= 3'h4;//4
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'hd;//c
cin <= 3'h3333;//3
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'ha;//b
cin <= 3'h2;//2
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'hb;//a
cin <= 3'h5;//5
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h8;//9
cin <= 3'h1;//1
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h9;//8
cin <= 3'h6;//6
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h6;//7
cin <= 3'h1;//1
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h7;//6
cin <= 3'h6;//6
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h4;//5
cin <= 3'h2;//2
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h5;//4
cin <= 3'h5;//5
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h2;//3
cin <= 3'h4;//4
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h3;//2
cin <= 3'h3;//3
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h0;//1
cin <= 3'h7;//7
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h1;//0
cin <= 3'h0;//0
#100
req <= 1'b0;
//***********************************correct datain************************
#200 req <= 1'b1;
datain <= 4'hf;//f
cin <= 3'h7;//7
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'he;//e
cin <= 3'h0;//0
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'hd;//d
cin <= 3'h4;//4
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'hc;//c
cin <= 3'h3;//3
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'hb;//b
cin <= 3'h2;//2
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'ha;//a
cin <= 3'h5;//5
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h9;//9
cin <= 3'h1;//1
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h8;//8
cin <= 3'h6;//6
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h7;//7
cin <= 3'h1;//1
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h6;//6
cin <= 3'h6;//6
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h5;//5
cin <= 3'h2;//2
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h4;//4
cin <= 3'h5;//5
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h3;//3
cin <= 3'h4;//4
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h2;//2
cin <= 3'h3;//3
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h1;//1
cin <= 3'h7;//7
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h0;//0
cin <= 3'h0;//0
#100
req <= 1'b0;
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h3;//0
cin <= 3'h7;//0
#100
req <= 1'b0;
#500000 $stop;
end
initial
begin
$dumpfile("Ham_Code_RT.vcd");
$dumpvars(0,Ham_Code_RT);
#500000 $finish;
end //end initial
//*********************************************************
// TEST_sysclk
//*********************************************************
always #20 clk <= !clk;//clk -> 40us/clk cycle
Ham_Code_R hcr (
.clk (clk ),
.rst (rst ),
.req (req ),
.datain (datain ),
.cin (cin ),
.dataout (dataout),
.ack (ack )
);
endmodule ⌨️ 快捷键说明
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