ham_code.v

来自「HAMMING CODE在偵錯及更正的原理實現」· Verilog 代码 · 共 70 行

`timescale 1ns/1ns

module Ham_Code (clk, rst, ,ack, datain, cout, dataout, req);

//input	signal
input 		clk,rst;
input		ack;
input	[3:0]	datain;

//output signal
output	[3:0]	dataout;
output		req;
output	[2:0]	cout;

wire	[3:0]	dataout;
wire		req;
wire	[2:0]	cout;

wire 		c1 = datain[3] ^ datain [2] ^ datain [0];
wire		c2 = datain[3] ^ datain [1] ^ datain [0];
wire		c3 = datain[2] ^ datain [1] ^ datain [0];

reg		h1,h2,h3,h4,h5,h6,h7;

always @(posedge clk or negedge rst)begin
	if (~rst)
		begin
		h1 <= 'bx;
		h2 <= 'bx;
		h3 <= 'bx;
		h4 <= 'bx;
		h5 <= 'bx;
		h6 <= 'bx;
		h7 <= 'bx;
		end
	else
		if (ack)
		begin
		h1 <=	 c1;		
                h2 <=    c2;
                h3 <=    datain[3] ;
                h4 <=	 c3;
                h5 <=    datain[2] ;
	        h6 <=	 datain[1] ;
                h7 <=	 datain[0] ;
		end
end

//**********************************************************
//			req
//**********************************************************

reg	reqs;

always @(posedge clk or negedge rst)begin
	if  (~rst)
	reqs <= 1'b1;
	else
	reqs <= ~ack;
end

assign req = reqs;

assign cout = {h1,h2,h4};

assign dataout = {h3,h5,h6,h7};

endmodule