ham_code_r.v

HAMMING CODE在偵錯及更正的原理實現

`timescale 1ns/1ns                                                             
                                                                               
module Ham_Code_R(clk, rst, req, cin, datain, dataout, ack);                      
//input	signal                                                                 
input 		clk,rst;                                                       
input		req;                                                           
input	[3:0]	datain;             
input	[2:0]	cin;                                           
                                                                               
//output signal                                                                
output	[3:0]	dataout;                                                     
output		ack;                                                           
                                                                               
wire	[3:0]	dataout;                                                     
wire		ack;                                                           
                                                                               
reg		h1,h2,h3,h4,h5,h6,h7;                                          

reg	[1:0]	st,st_next;
                                                                                                              
parameter [1:0]  ST0 = 2'b00,// IDLE (received cin & datain)           
                 ST1 = 2'b01,// Calculated                                  
                 ST2 = 2'b10,// Check                                 
                 ST3 = 2'b11;// updated & finish 

reg	[3:0]	tempdin;

reg	[2:0]	tempcin;

always @(st or req or datain or cin)begin
	case (st)	
		ST0:	if (req)
				begin
				tempdin <= datain;					
				tempcin <= cin;
				st_next <= ST1;
				end
			else
				begin
				tempdin <= 'bx;
				tempcin <= 'bx;
				st_next <= ST0;
				end
					
		ST1:		st_next <= ST2;	
		
		ST2:		st_next <= ST3;
		
		ST3:		st_next <= ST0;
		default:	st_next <= ST0;
	endcase
end		
	

always @(posedge clk or negedge rst)begin
	if (~rst)
		st <= ST0;
	else
		st <= st_next;
end                       

reg	c_1,c_2,c_3;

always @(posedge clk or negedge rst)begin
	if (~rst)
	begin
	c_1 = 'bx;
        c_2 = 'bx;
        c_3 = 'bx;
        end
        else
        if (st == ST1)
        begin
        c_1 = tempdin[3] ^ tempdin [2] ^ tempdin [0];
        c_2 = tempdin[3] ^ tempdin [1] ^ tempdin [0];
        c_3 = tempdin[2] ^ tempdin [1] ^ tempdin [0];
        end
end

reg	[2:0]	cherr;//0:correct 1:error


always @(posedge clk or negedge rst)begin
	if (~rst)
	cherr <= 'bx;
	else
		if(st == ST2)
		begin
		cherr [2] = tempcin[2] ^ c_1;
		cherr [1] = tempcin[1] ^ c_2;
		cherr [0] = tempcin[0] ^ c_3;		
		end
		else
		begin
		cherr = cherr;
		end
end

reg	acks;

always @(posedge clk or negedge rst)begin
	if (~rst)
	acks <= 1'b1;
	else
		if (st == ST3)
		acks <= 1'b0;
		else
		acks <= 1'b1;
end

reg	[3:0]	data_out;

always @(posedge clk or negedge rst)begin
	if (~rst)
	begin
	data_out <= 'hx;
	end
	else
	begin
		if (st == ST3)
			case (cherr)				
			3'b011: data_out <= {~tempdin[3], tempdin[2], tempdin[1], tempdin[0]};
			3'b101: data_out <= { tempdin[3],~tempdin[2], tempdin[1], tempdin[0]};
			3'b110: data_out <= { tempdin[3], tempdin[2],~tempdin[1], tempdin[0]};
			3'b111: data_out <= { tempdin[3], tempdin[2], tempdin[1],~tempdin[0]};
			default: data_out <= tempdin;
			endcase
		else
			data_out <= data_out;
	end
	
end

assign  dataout = data_out;

assign  ack = acks;

endmodule