📄 ham_code_16rt.v
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`timescale 1ns/1ns
module Ham_Code_16RT();
//input signal
reg clk,rst;
reg req;
reg [15:0] datain;
reg [11:0] cin;
//output signal
wire [15:0] dataout;
wire ack;
//**********************************************************
// 1111 f 1110 => e
// 1110 e 1110 => f
// 1101 d 1100 => c
// 1100 c 1101 => d
// 1011 b 1010 => a
// 1010 a 1011 => b
// 1001 9 1000 => 8
// 1000 8 1001 => 9
// 0111 7 0110 => 7
// 0110 6 0111 => 6
// 0101 5 0100 => 4
// 0100 4 0101 => 5
// 0011 3 0010 => 2
// 0010 2 0011 => 3
// 0001 1 0000 => 0
// 0000 0 0001 => 1
//*************************************************************
initial
begin
#10 clk <= 0;
rst <= 0;
req <= 0;
#100 rst <= 1;
#200 req <= 1'b1;
datain <= 16'heeee;//f
cin <= 12'hfff;//7
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'hffff;//e
cin <= 12'h0;//0
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'hcccc;//d
cin <= 12'h924;//4
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'hdddd;//c
cin <= 12'h6db;//3
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'haaaa;//b
cin <= 12'h492;//2
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'hbbbb;//a
cin <= 12'hb6d;//5
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h8888;//9
cin <= 12'h249;//1
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h9999;//8
cin <= 12'hdb6;//6
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h6666;//7
cin <= 12'h249;//1
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h7777;//6
cin <= 12'hdb6;//6
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h4444;//5
cin <= 12'h492;//2
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h5555;//4
cin <= 12'hb6d;//5
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h2222;//3
cin <= 12'h924;//4
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h3333;//2
cin <= 12'h6db;//3
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h0000;//1
cin <= 12'hfff;//7
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h1111;//0
cin <= 12'h0;//0
#100
req <= 1'b0;
//***********************************correct datain************************
#200 req <= 1'b1;
datain <= 16'hffff;//f
cin <= 12'hfff;//7
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'heeee;//e
cin <= 12'h0;//0
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'hdddd;//d
cin <= 12'h924;//4
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'hcccc;//c
cin <= 12'h6db;//3
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'hbbbb;//b
cin <= 12'h492;//2
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'haaaa;//a
cin <= 12'hb6d;//5
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h9999;//9
cin <= 12'h249;//1
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h8888;//8
cin <= 12'hdb6;//6
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h7777;//7
cin <= 12'h249;//1
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h6666;//6
cin <= 12'hdb6;//6
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 4'h5555;//5
cin <= 3'h492;//2
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h4444;//4
cin <= 12'hb6d;//5
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h3333;//3
cin <= 12'h924;//4
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h2222;//2
cin <= 12'h6db;//3
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h1111;//1
cin <= 12'hfff;//7
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h0000;//0
cin <= 12'h0;//0
#100
req <= 1'b0;
#100
req <= 1'b0;
#200 req <= 1'b1;
datain <= 16'h3333;//0
cin <= 12'hfff;//0
#100
req <= 1'b0;
#500000 $stop;
end
initial
begin
$dumpfile("Ham_Code_16RT.vcd");
$dumpvars(0,Ham_Code_16RT);
#500000 $finish;
end //end initial
//*********************************************************
// TEST_sysclk
//*********************************************************
always #20 clk <= !clk;//clk -> 40us/clk cycle
Ham_Code_16R hcr16 (
.clk (clk ),
.rst (rst ),
.req (req ),
.datain (datain ),
.cin (cin ),
.dataout (dataout),
.ack (ack )
);
endmodule ⌨️ 快捷键说明
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