bufio.v

HAMMING CODE在偵錯及更正的原理實現

`timescale 1ns/1ns
//*********************** 16 x 16 BUFIO *************************
//
//
//***************************************************************
module BUFIO (clk, rst, datain, req, fulls, dataout, ack, emptys, mids);

//input signal

input		clk;
input		rst;
input		req;
input	[15:0]	datain;

//output signal

output 		ack;
output		fulls;
output	[15:0]	dataout;
output		emptys;
output		mids;

wire 		ack;            
wire		fulls;          
wire	[15:0]	dataout;   
wire		emptys;         
wire		mids;           

//reg	[15:0]	temp_1,temp_2,temp_3,temp_4,temp_5,temp_6,temp_7,temp_8;
reg	[15:0]	temp;//temp_13,temp_14,temp_15,temp_16;
reg	[3:0]	counter;
//reg 		encnt;

always @(posedge clk or negedge rst)begin
	if (~rst)
	counter <= 'bx;
	else
		if (req)
		counter <= counter + 1'b1;
		else
	 	counter <= counter;
end

reg	[15:0]	data_out;

always @(posedge clk)begin
	if (req)
	data_out [counter] <= datain;
	else
	data_out [counter] <= data_out[counter];
end	
	
always @(posedge clk)begin 	
	case(counter)
		4'h0:	temp  <= data_out[counter];
		4'h1:	temp  <= data_out[counter];
		4'h2:	temp  <= data_out[counter];
		4'h3:	temp  <= data_out[counter];
		4'h4:	temp  <= data_out[counter];
		4'h5:	temp  <= data_out[counter];
		4'h6:	temp  <= data_out[counter];
		4'h7:	temp  <= data_out[counter];
		4'h8:	temp  <= data_out[counter];
		4'h9:	temp  <= data_out[counter];
		4'ha:	temp  <= data_out[counter];
		4'hb:	temp  <= data_out[counter];
		4'hc:	temp  <= data_out[counter];
		4'hd:	temp  <= data_out[counter];
		4'he:	temp  <= data_out[counter];
		4'hf:	temp  <= data_out[counter];
		default:
		        temp  <= temp;  	
		endcase
end
			



//***************************************************************
//			full signal
//                        
//***************************************************************

reg	full_s;

always @(posedge clk)begin
	if (~rst)
	full_s <= 1'b0;
	else
	full_s = (counter == 4'hf)? 1'b1:1'b0;
end


//*************************************************************** 			 
//			empty signal                                 
//                                                                  
//***************************************************************   

reg	empty_s;                                                     

always @(posedge clk)begin                                          
	if (~rst)                                                   
	empty_s <= 1'b0;                                             
	else                                                        
	empty_s =(counter == 4'h0)? 1'b1:1'b0;                                
end                                                                 
  
  
//***************************************************************   
//			mid signal                               
//                                                                
//*************************************************************** 

reg	mid_s;                                                   

always @(posedge clk)begin                                        
	if (~rst)                                                 
	mid_s <= 1'b0;                                           
	else                                                      
	mid_s = (counter == 4'h8)? 1'b1:1'b0;                            
end                                

//*************************************************************
//			ack signal 
//
//*************************************************************

reg	ack_s;

always @(posedge clk)begin
	if (~rst)
	ack_s <= 1'b0;
	else
	ack_s <= (|counter)? 1'b1:1'b0;
end		 

//*************************************************************
//			
//
//*************************************************************


assign dataout = temp;
assign ack = ack_s;
assign fulls = full_s;
assign emptys = empty_s;
assign mids = mid_s;

endmodule