ham_code_tt.v

HAMMING CODE在偵錯及更正的原理實現

`timescale 1ns/1ns                                                             
                                                                               
module Ham_Code_TT();

//input	signal                                                                 
reg 		clk,rst;                                                       
reg		ack;                                                           
reg	[3:0]	datain;                                                        
                                                                               
//output signal                                                                
wire	[3:0]	dataout;                                                     
wire		req;                                                           
wire	[2:0]	cout;	                

initial                                                      
begin                                                        
#10 		clk  	<= 0;                                
		rst  	<= 0;
#100		ack	<=1'b0;
		datain 	<= 4'hf;//f                                
#200		rst  	<= 1;     
		ack  	<= 1'b1;  
#100		ack	<=1'b0;      
		datain 	<= 4'he;//e      
#200		//rst  	<= 1;           
		ack  	<= 1'b1;        		
#100		ack	<=1'b0;      
		datain 	<= 4'hd;//d      
#200		//rst  	<= 1;           
		ack  	<= 1'b1;        
#100		ack	<=1'b0;      
		datain 	<= 4'hc;//c      
#200		//rst  	<= 1;           
		ack  	<= 1'b1;        
#100		ack	<=1'b0;      
		datain 	<= 4'hb;//b      
#200		//rst  	<= 1;           
		ack  	<= 1'b1;        
#100		ack	<=1'b0;      
		datain 	<= 4'ha;//a      
#200		//rst  	<= 1;           
		ack  	<= 1'b1;        		                           
#100		ack	<=1'b0;      
		datain 	<= 4'h9;//9      
#200		//rst  	<= 1;           
		ack  	<= 1'b1;        
#100		ack	<=1'b0;      
		datain 	<= 4'h8;//8      
#200		//rst  	<= 1;           
		ack  	<= 1'b1;        
#100		ack	<=1'b0;      
		datain 	<= 4'h7;//7      
#200		//rst  	<= 1;           
		ack  	<= 1'b1;        
#100		ack	<=1'b0;      
		datain 	<= 4'h6;//6      
#200		//rst  	<= 1;           		                                             
		ack  	<= 1'b1;
#100		ack	<=1'b0;    
		datain 	<= 4'h5;//5   
#200		//rst  	<= 1;      
		ack  	<= 1'b1;   
#100		ack	<=1'b0;    
		datain 	<= 4'h4;//4   
#200		//rst  	<= 1;      
		ack  	<= 1'b1;   
#100		ack	<=1'b0;    
		datain 	<= 4'h3;//3   
#200		//rst  	<= 1;      
		ack  	<= 1'b1;   
#100		ack	<=1'b0;    
		datain 	<= 4'h2;//2   
#200		//rst  	<= 1;      
		ack  	<= 1'b1;   
#100		ack	<=1'b0;    
		datain 	<= 4'h1;//1   
#200		//rst  	<= 1;      
		ack  	<= 1'b1;   
#100		ack	<=1'b0;    
		datain 	<= 4'h0;//0   		
#200		//rst  	<= 1;      		
		ack  	<= 1'b1;   		
		
#500000 $stop;                                                
end                                                          
                                                             
initial                                                      
begin                                                        
     	$dumpfile("Ham_Code_TT.vcd");                           
        $dumpvars(0,Ham_Code_TT);                               
#500000 $finish;	                                             
                                                             
end //end initial                                            

//*********************************************************     
//                      TEST_sysclk                             
//*********************************************************     
                                                                
always  #20  clk <= !clk;//clk -> 40us/clk1 cycle      
	                
Ham_Code_T 	hamct	(
			 .clk		(clk	),
			 .rst		(rst	),
			 .ack		(ack	),
			 .datain	(datain	),
			 .cout		(cout	),
			 .dataout	(dataout),
			 .req		(req	)
			);
endmodule