ham_code_16t.v

HAMMING CODE在偵錯及更正的原理實現

`timescale 1ns/1ns                                               
                                                                 
module Ham_Code_16T (clk, rst, ack, datain, cout, dataout, req);
//input	signal                       
input 		clk,rst;                
input		ack;                 
input	[15:0]	datain;              
                                     
//output signal                      
output	[15:0]	dataout;             
output		req;                 
output	[11:0]	cout;
//wire	[15:0]	dataout;
//wire		req;

wire	[3:0]	dataina,datainb,datainc,dataind;
wire	[2:0]	couta,coutb,coutc,coutd;
wire	[3:0]	dataouta,dataoutb,dataoutc,dataoutd;

wire		req1,req2,req3,req4;		

wire		ack1 = ack;
wire		ack2 = ack;
wire		ack3 = ack;
wire		ack4 = ack;
//datain
assign	dataina = datain [ 3: 0]; 
assign	datainb = datain [ 7: 4];
assign	datainc = datain [11: 8];
assign	dataind = datain [15:12];
//cout
assign	couta	= cout [ 2:0]; 
assign	coutb	= cout [ 5:3]; 
assign	coutc	= cout [ 8:6]; 
assign	coutd	= cout [11:9]; 
//dataout
assign 	dataout[ 3: 0] = dataouta; 
assign 	dataout[ 7: 4] = dataoutb;
assign 	dataout[11: 8] = dataoutc;
assign 	dataout[15:12] = dataoutd;

wire	req  = req1 | req2 | req3 | req4;

Ham_Code_T 	H1(
		   .clk		(clk		),
		   .rst		(rst		),
		   .ack		(ack1		),
		   .datain	(dataina	),
		   .cout	(couta		),
		   .dataout	(dataouta	),
		   .req		(req1		)
		   );         	             
		   
Ham_Code_T 	H2(                                 		   
		   .clk		(clk		),  
		   .rst		(rst		),  
		   .ack		(ack2		),  
		   .datain	(datainb	),  
		   .cout	(coutb	        ),  
		   .dataout	(dataoutb       ),  
		   .req		(req2		)   
		   );         	                    

Ham_Code_T 	H3(                                 		   
		   .clk		(clk		),  		   
		   .rst		(rst		),  
		   .ack		(ack3		),  
		   .datain	(datainc        ),  
		   .cout	(coutc	        ),  
		   .dataout	(dataoutc       ),  
		   .req		(req3		)   
		   );         	                    

Ham_Code_T 	H4(                                 		   
		   .clk		(clk		),  
		   .rst		(rst		),  
		   .ack		(ack4		),  
		   .datain	(dataind        ),  
		   .cout	(coutd          ),  
		   .dataout	(dataoutd       ),  
		   .req		(req4		)   
		   );         	               

endmodule