dac0832.tan.rpt

由VHDL 语言实现的DA0832器利用的是QUARTUES环境已经得到验证

; tco                                                                    ;
+-------+--------------+------------+---------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To          ; From Clock ;
+-------+--------------+------------+---------+-------------+------------+
; N/A   ; None         ; 7.556 ns   ; data[2] ; data_out[2] ; clk        ;
; N/A   ; None         ; 7.490 ns   ; data[1] ; data_out[1] ; clk        ;
; N/A   ; None         ; 7.049 ns   ; data[7] ; data_out[7] ; clk        ;
; N/A   ; None         ; 6.881 ns   ; data[4] ; data_out[4] ; clk        ;
; N/A   ; None         ; 6.522 ns   ; data[3] ; data_out[3] ; clk        ;
; N/A   ; None         ; 6.493 ns   ; data[0] ; data_out[0] ; clk        ;
; N/A   ; None         ; 6.417 ns   ; data[6] ; data_out[6] ; clk        ;
; N/A   ; None         ; 6.407 ns   ; data[5] ; data_out[5] ; clk        ;
+-------+--------------+------------+---------+-------------+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To      ; To Clock ;
+---------------+-------------+-----------+------+---------+----------+
; N/A           ; None        ; -1.567 ns ; rst  ; data[0] ; clk      ;
; N/A           ; None        ; -1.567 ns ; rst  ; data[1] ; clk      ;
; N/A           ; None        ; -1.567 ns ; rst  ; data[2] ; clk      ;
; N/A           ; None        ; -1.567 ns ; rst  ; data[3] ; clk      ;
; N/A           ; None        ; -1.567 ns ; rst  ; data[4] ; clk      ;
; N/A           ; None        ; -1.567 ns ; rst  ; data[5] ; clk      ;
; N/A           ; None        ; -1.567 ns ; rst  ; data[6] ; clk      ;
; N/A           ; None        ; -1.567 ns ; rst  ; data[7] ; clk      ;
+---------------+-------------+-----------+------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sun Aug 12 15:12:24 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DAC0832 -c DAC0832 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 271.52 MHz between source register "q[2]" and destination register "data[0]" (period= 3.683 ns)
    Info: + Longest register to register delay is 3.422 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N3; Fanout = 4; REG Node = 'q[2]'
        Info: 2: + IC(0.763 ns) + CELL(0.590 ns) = 1.353 ns; Loc. = LC_X2_Y2_N9; Fanout = 1; COMB Node = 'data[0]~363'
        Info: 3: + IC(0.449 ns) + CELL(0.292 ns) = 2.094 ns; Loc. = LC_X2_Y2_N8; Fanout = 8; COMB Node = 'data[0]~364'
        Info: 4: + IC(0.461 ns) + CELL(0.867 ns) = 3.422 ns; Loc. = LC_X2_Y2_N0; Fanout = 4; REG Node = 'data[0]'
        Info: Total cell delay = 1.749 ns ( 51.11 % )
        Info: Total interconnect delay = 1.673 ns ( 48.89 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.730 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y2_N0; Fanout = 4; REG Node = 'data[0]'
            Info: Total cell delay = 2.180 ns ( 79.85 % )
            Info: Total interconnect delay = 0.550 ns ( 20.15 % )
        Info: - Longest clock path from clock "clk" to source register is 2.730 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X3_Y2_N3; Fanout = 4; REG Node = 'q[2]'
            Info: Total cell delay = 2.180 ns ( 79.85 % )
            Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "data[0]" (data pin = "rst", clock pin = "clk") is 1.619 ns
    Info: + Longest pin to register delay is 4.312 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; PIN Node = 'rst'
        Info: 2: + IC(1.073 ns) + CELL(0.442 ns) = 2.984 ns; Loc. = LC_X2_Y2_N8; Fanout = 8; COMB Node = 'data[0]~364'
        Info: 3: + IC(0.461 ns) + CELL(0.867 ns) = 4.312 ns; Loc. = LC_X2_Y2_N0; Fanout = 4; REG Node = 'data[0]'
        Info: Total cell delay = 2.778 ns ( 64.42 % )
        Info: Total interconnect delay = 1.534 ns ( 35.58 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y2_N0; Fanout = 4; REG Node = 'data[0]'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
Info: tco from clock "clk" to destination pin "data_out[2]" through register "data[2]" is 7.556 ns
    Info: + Longest clock path from clock "clk" to source register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y2_N2; Fanout = 4; REG Node = 'data[2]'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.602 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y2_N2; Fanout = 4; REG Node = 'data[2]'
        Info: 2: + IC(2.494 ns) + CELL(2.108 ns) = 4.602 ns; Loc. = PIN_144; Fanout = 0; PIN Node = 'data_out[2]'
        Info: Total cell delay = 2.108 ns ( 45.81 % )
        Info: Total interconnect delay = 2.494 ns ( 54.19 % )
Info: th for register "data[0]" (data pin = "rst", clock pin = "clk") is -1.567 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y2_N0; Fanout = 4; REG Node = 'data[0]'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 4.312 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; PIN Node = 'rst'
        Info: 2: + IC(1.073 ns) + CELL(0.442 ns) = 2.984 ns; Loc. = LC_X2_Y2_N8; Fanout = 8; COMB Node = 'data[0]~364'
        Info: 3: + IC(0.461 ns) + CELL(0.867 ns) = 4.312 ns; Loc. = LC_X2_Y2_N0; Fanout = 4; REG Node = 'data[0]'
        Info: Total cell delay = 2.778 ns ( 64.42 % )
        Info: Total interconnect delay = 1.534 ns ( 35.58 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 106 megabytes of memory during processing
    Info: Processing ended: Sun Aug 12 15:12:26 2007
    Info: Elapsed time: 00:00:02