pulse.tan.rpt

由VHDL 语言实现的数控分频 利用的是QUARTUES环境已经得到验证

+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+------+----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To             ; To Clock ;
+---------------+-------------+-----------+------+----------------+----------+
; N/A           ; None        ; -0.157 ns ; d[6] ; \p_reg:cnt8[6] ; clk      ;
; N/A           ; None        ; -3.938 ns ; d[7] ; \p_reg:cnt8[7] ; clk      ;
; N/A           ; None        ; -3.940 ns ; d[4] ; \p_reg:cnt8[4] ; clk      ;
; N/A           ; None        ; -4.157 ns ; d[2] ; \p_reg:cnt8[2] ; clk      ;
; N/A           ; None        ; -4.199 ns ; d[0] ; \p_reg:cnt8[0] ; clk      ;
; N/A           ; None        ; -4.822 ns ; d[5] ; \p_reg:cnt8[5] ; clk      ;
; N/A           ; None        ; -4.827 ns ; d[3] ; \p_reg:cnt8[3] ; clk      ;
; N/A           ; None        ; -5.049 ns ; d[1] ; \p_reg:cnt8[1] ; clk      ;
+---------------+-------------+-----------+------+----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu Aug 02 21:40:35 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pulse -c pulse --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "full" as buffer
Info: Clock "clk" has Internal fmax of 259.47 MHz between source register "\p_reg:cnt8[7]" and destination register "\p_reg:cnt8[2]" (period= 3.854 ns)
    Info: + Longest register to register delay is 3.593 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y3_N7; Fanout = 2; REG Node = '\p_reg:cnt8[7]'
        Info: 2: + IC(0.552 ns) + CELL(0.590 ns) = 1.142 ns; Loc. = LC_X8_Y3_N9; Fanout = 2; COMB Node = 'Equal0~65'
        Info: 3: + IC(0.462 ns) + CELL(0.292 ns) = 1.896 ns; Loc. = LC_X8_Y3_N8; Fanout = 8; COMB Node = 'Equal0~66'
        Info: 4: + IC(0.472 ns) + CELL(1.225 ns) = 3.593 ns; Loc. = LC_X8_Y3_N2; Fanout = 5; REG Node = '\p_reg:cnt8[2]'
        Info: Total cell delay = 2.107 ns ( 58.64 % )
        Info: Total interconnect delay = 1.486 ns ( 41.36 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.730 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X8_Y3_N2; Fanout = 5; REG Node = '\p_reg:cnt8[2]'
            Info: Total cell delay = 2.180 ns ( 79.85 % )
            Info: Total interconnect delay = 0.550 ns ( 20.15 % )
        Info: - Longest clock path from clock "clk" to source register is 2.730 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X8_Y3_N7; Fanout = 2; REG Node = '\p_reg:cnt8[7]'
            Info: Total cell delay = 2.180 ns ( 79.85 % )
            Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "\p_reg:cnt8[1]" (data pin = "d[1]", clock pin = "clk") is 5.101 ns
    Info: + Longest pin to register delay is 7.794 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_134; Fanout = 1; PIN Node = 'd[1]'
        Info: 2: + IC(6.204 ns) + CELL(0.115 ns) = 7.794 ns; Loc. = LC_X8_Y3_N1; Fanout = 4; REG Node = '\p_reg:cnt8[1]'
        Info: Total cell delay = 1.590 ns ( 20.40 % )
        Info: Total interconnect delay = 6.204 ns ( 79.60 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X8_Y3_N1; Fanout = 4; REG Node = '\p_reg:cnt8[1]'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
Info: tco from clock "clk" to destination pin "fout" through register "\p_div:cnt2" is 8.559 ns
    Info: + Longest clock path from clock "clk" to source register is 4.441 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X8_Y3_N8; Fanout = 1; REG Node = 'full'
        Info: 3: + IC(0.776 ns) + CELL(0.711 ns) = 4.441 ns; Loc. = LC_X7_Y3_N2; Fanout = 2; REG Node = '\p_div:cnt2'
        Info: Total cell delay = 3.115 ns ( 70.14 % )
        Info: Total interconnect delay = 1.326 ns ( 29.86 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.894 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N2; Fanout = 2; REG Node = '\p_div:cnt2'
        Info: 2: + IC(1.770 ns) + CELL(2.124 ns) = 3.894 ns; Loc. = PIN_32; Fanout = 0; PIN Node = 'fout'
        Info: Total cell delay = 2.124 ns ( 54.55 % )
        Info: Total interconnect delay = 1.770 ns ( 45.45 % )
Info: th for register "\p_reg:cnt8[6]" (data pin = "d[6]", clock pin = "clk") is -0.157 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X8_Y3_N6; Fanout = 4; REG Node = '\p_reg:cnt8[6]'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 2.902 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 1; PIN Node = 'd[6]'
        Info: 2: + IC(1.318 ns) + CELL(0.115 ns) = 2.902 ns; Loc. = LC_X8_Y3_N6; Fanout = 4; REG Node = '\p_reg:cnt8[6]'
        Info: Total cell delay = 1.584 ns ( 54.58 % )
        Info: Total interconnect delay = 1.318 ns ( 45.42 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 106 megabytes of memory during processing
    Info: Processing ended: Thu Aug 02 21:40:37 2007
    Info: Elapsed time: 00:00:02