📄 dff1.tan.rpt
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Classic Timing Analyzer report for dff1
Sat Jul 21 07:20:11 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.670 ns ; d ; q1 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.491 ns ; q1 ; q ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -3.618 ns ; d ; q1 ; -- ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+----+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+----+----------+
; N/A ; None ; 3.670 ns ; d ; q1 ; clk ;
+-------+--------------+------------+------+----+----------+
+------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+----+------------+
; N/A ; None ; 6.491 ns ; q1 ; q ; clk ;
+-------+--------------+------------+------+----+------------+
+----------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+----+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+----+----------+
; N/A ; None ; -3.618 ns ; d ; q1 ; clk ;
+---------------+-------------+-----------+------+----+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Sat Jul 21 07:20:08 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dff1 -c dff1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "q1" (data pin = "d", clock pin = "clk") is 3.670 ns
Info: + Longest pin to register delay is 6.632 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 1; PIN Node = 'd'
Info: 2: + IC(5.048 ns) + CELL(0.115 ns) = 6.632 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q1'
Info: Total cell delay = 1.584 ns ( 23.88 % )
Info: Total interconnect delay = 5.048 ns ( 76.12 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "clk" to destination register is 2.999 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.819 ns) + CELL(0.711 ns) = 2.999 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q1'
Info: Total cell delay = 2.180 ns ( 72.69 % )
Info: Total interconnect delay = 0.819 ns ( 27.31 % )
Info: tco from clock "clk" to destination pin "q" through register "q1" is 6.491 ns
Info: + Longest clock path from clock "clk" to source register is 2.999 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.819 ns) + CELL(0.711 ns) = 2.999 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q1'
Info: Total cell delay = 2.180 ns ( 72.69 % )
Info: Total interconnect delay = 0.819 ns ( 27.31 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 3.268 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q1'
Info: 2: + IC(1.144 ns) + CELL(2.124 ns) = 3.268 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'q'
Info: Total cell delay = 2.124 ns ( 64.99 % )
Info: Total interconnect delay = 1.144 ns ( 35.01 % )
Info: th for register "q1" (data pin = "d", clock pin = "clk") is -3.618 ns
Info: + Longest clock path from clock "clk" to destination register is 2.999 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.819 ns) + CELL(0.711 ns) = 2.999 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q1'
Info: Total cell delay = 2.180 ns ( 72.69 % )
Info: Total interconnect delay = 0.819 ns ( 27.31 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 6.632 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 1; PIN Node = 'd'
Info: 2: + IC(5.048 ns) + CELL(0.115 ns) = 6.632 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q1'
Info: Total cell delay = 1.584 ns ( 23.88 % )
Info: Total interconnect delay = 5.048 ns ( 76.12 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 106 megabytes of memory during processing
Info: Processing ended: Sat Jul 21 07:20:12 2007
Info: Elapsed time: 00:00:04
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