aes_tb_test2.vhd

VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits

-------------------------------------------------------------------------------
-- Title      : A compact 8bit AES encryption core
-------------------------------------------------------------------------------
-- File       : aes_tb_test2.vhd
-- Author     : Timo Alho  <[e-mail]>
-- Date       : 27.2.2006
-------------------------------------------------------------------------------
-- Description: Testbench for design "aes".  This testbench test that
-- loading new data and unloading old result simultaneously works
-- correcly
-------------------------------------------------------------------------------
-- Disclaimer: The AES encryption core provided here is distributed AS
-- IS without any warranty of any kind either expressed or implied,
-- including, without limitation, warranties of merchantability,
-- fitness for a particular purpose or non infringement of
-- intellectual property rights.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

architecture test2 of aes_tb is

  component aes
    port (
      clk        : in  std_logic;
      rst_n      : in  std_logic;
      data_in    : in  std_logic_vector(7 downto 0);
      data_out   : out std_logic_vector(7 downto 0);
      key_in     : in  std_logic_vector(7 downto 0);
      load_in    : in  std_logic;
      unload_in  : in  std_logic;
      start_in   : in  std_logic;
      inverse_in : in  std_logic;
      busy_out   : out std_logic);
  end component;

  -- component ports
  signal clk        : std_logic := '0';
  signal rst_n      : std_logic;
  signal data_in    : std_logic_vector(7 downto 0);
  signal data_out   : std_logic_vector(7 downto 0);
  signal key_in     : std_logic_vector(7 downto 0);
  signal load_in    : std_logic;
  signal unload_in  : std_logic;
  signal start_in   : std_logic;
  signal inverse_in : std_logic;
  signal busy_out   : std_logic;

  type testvec_t is array (0 to 15) of integer range 0 to 255;

  constant key_fwd : testvec_t :=
    (16#00#, 16#01#, 16#02#, 16#03#, 16#04#, 16#05#, 16#06#, 16#07#,
     16#08#, 16#09#, 16#0a#, 16#0b#, 16#0c#, 16#0d#, 16#0e#, 16#0f#);

  constant ptext : testvec_t :=
    (16#00#, 16#11#, 16#22#, 16#33#, 16#44#, 16#55#, 16#66#, 16#77#,
     16#88#, 16#99#, 16#aa#, 16#bb#, 16#cc#, 16#dd#, 16#ee#, 16#ff#);

  constant ctext : testvec_t :=
    (16#69#, 16#c4#, 16#e0#, 16#d8#, 16#6a#, 16#7b#, 16#04#, 16#30#,
     16#d8#, 16#cd#, 16#b7#, 16#80#, 16#70#, 16#b4#, 16#c5#, 16#5a#);

begin  -- architecture test2

  DUT : aes
    port map (
      clk        => clk,
      rst_n      => rst_n,
      data_in    => data_in,
      data_out   => data_out,
      key_in     => key_in,
      load_in    => load_in,
      unload_in  => unload_in,
      start_in   => start_in,
      inverse_in => inverse_in,
      busy_out   => busy_out);

  -- clock generation
  clk <= not clk after 5 ns;            -- 100 MHz clock

  gen_reset : process
  begin
    rst_n <= '0';
    wait for 10 ns;
    rst_n <= '1';
    wait;
  end process gen_reset;


  -- waveform generation
  WaveGen_Proc : process
    variable t : integer;
  begin
    -- insert signal assignments here
    data_in   <= (others => '0');
    key_in    <= (others => '0');
    load_in   <= '0';
    unload_in <= '0';

    inverse_in <= '0';
    start_in   <= '0';

    -- wait reset
    wait until rising_edge(clk) and rst_n = '1';

    -- few idle cycles
    for t in 0 to 1 loop
      wait until rising_edge(clk);
    end loop;  -- t

    ---------------------------------------------------------------------------
    -- 1st load
    ---------------------------------------------------------------------------
    for i in 0 to 15 loop
      wait until falling_edge(clk);
      load_in <= '1';
      data_in <= std_logic_vector(to_unsigned(ptext(i), 8));
      key_in  <= std_logic_vector(to_unsigned(key_fwd(i), 8));
      wait until rising_edge(clk);
    end loop;  -- i
    load_in  <= '0';
    wait until rising_edge(clk);
    start_in <= '1';
    wait until rising_edge(clk);
    start_in <= '0';

    for j in 0 to 14 loop

      -- compute
      wait until rising_edge(clk) and busy_out = '0';

      -------------------------------------------------------------------------
      -- read j bytes of output, then start loading the input
      -------------------------------------------------------------------------
      for i in 0 to j loop
        wait until falling_edge(clk);
        unload_in <= '1';
        wait until rising_edge(clk);
        assert ctext(i) = to_integer(unsigned(data_out))
          report "test failed" severity error;
      end loop;  -- i
      --read rest of output, load input
      for i in j+1 to 15 loop
        wait until falling_edge(clk);
        unload_in <= '1';
        load_in   <= '1';
        data_in   <= std_logic_vector(to_unsigned(ptext(i-(j+1)), 8));
        key_in    <= std_logic_vector(to_unsigned(key_fwd(i-(j+1)), 8));
        wait until rising_edge(clk);
        assert ctext(i) = to_integer(unsigned(data_out))
          report "test failed" severity error;
      end loop;  -- i
      unload_in <= '0';
      for i in 15-j to 15 loop
        wait until falling_edge(clk);
        load_in <= '1';
        data_in <= std_logic_vector(to_unsigned(ptext(i), 8));
        key_in  <= std_logic_vector(to_unsigned(key_fwd(i), 8));
        wait until rising_edge(clk);
      end loop;  -- i
      load_in  <= '0';
      wait until rising_edge(clk);
      start_in <= '1';
      wait until rising_edge(clk);
      start_in <= '0';
    end loop;  -- j


    -- compute
    wait until rising_edge(clk) and busy_out = '0';

    for i in 0 to 15 loop
      wait until falling_edge(clk);
      unload_in <= '1';
      wait until rising_edge(clk);
      assert ctext(i) = to_integer(unsigned(data_out))
        report "test failed" severity error;
    end loop;  -- i

    report "tests done!" severity warning;
    wait;
  end process WaveGen_Proc;

  
end architecture test2;