zonghe.map.rpt

对PCM编码的多路复用与解复用程序

; Total registers      ; 46                   ;
; I/O pins             ; 12                   ;
; Maximum fan-out node ; count[5]             ;
; Maximum fan-out      ; 38                   ;
; Total fan-out        ; 162                  ;
; Average fan-out      ; 2.61                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |ZongHe                    ; 50         ; 12   ; |ZongHe             ;
+----------------------------+------------+------+---------------------+


+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 ;
+------------------------+-------------+----------------------------+
; Parameter Name         ; Value       ; Type                       ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH              ; 16          ; Untyped                    ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                    ;
; LPM_DIRECTION          ; ADD         ; Untyped                    ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                    ;
; LPM_PIPELINE           ; 0           ; Untyped                    ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                    ;
; REGISTERED_AT_END      ; 0           ; Untyped                    ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                    ;
; USE_CS_BUFFERS         ; 1           ; Untyped                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH         ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                    ;
; USE_WYS                ; OFF         ; Untyped                    ;
; STYLE                  ; FAST        ; Untyped                    ;
; CBXI_PARAMETER         ; add_sub_aph ; Untyped                    ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE             ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Jun 01 22:41:10 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ZongHe -c ZongHe
Info: Found 1 design units, including 1 entities, in source file ZongHe.v
    Info: Found entity 1: ZongHe
Info: Elaborating entity "ZongHe" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at ZongHe.v(31): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at ZongHe.v(71): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at ZongHe.v(75): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at ZongHe.v(76): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at ZongHe.v(77): truncated value with size 32 to match size of target (1)
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[1]", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "16"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "16"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "16"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "16"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "16"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "16"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Ignored 11 buffer(s)
    Info: Ignored 11 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "ClkIn" to global clock signal
Info: Implemented 62 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 7 output pins
    Info: Implemented 50 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Fri Jun 01 22:41:12 2007
    Info: Elapsed time: 00:00:02