shift.vhd

来自「16位CUPIP核,完全运行的好的东西,可以直接拿来用的!」· VHDL 代码 · 共 23 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cpu_lib.all;
entity shift is
port ( a : in bit16;
	 sel : in t_shift ;
	   y : out bit16);
end shift;
architecture rtl of shift is
begin
shftproc: process(a, sel)
begin
case sel is
when shftpass =>y <= a after 1 ns;
when sftl =>y <= a(14 downto 0) & '0' after 1 ns;
when sftr =>y <= '0' & a(15 downto 1) after 1 ns;
when rotl =>y <= a(14 downto 0) & a(15) after 1 ns;
when rotr =>y <= a(0) & a(15 downto 1) after 1 ns;
when others =>y <= "0000000000000000" after 1 ns;
end case;
end process;
end rtl;