top.tan.rpt

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                                    ; From                                                                ; To                                                                                                                                                                                                     ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 13.547 ns                                      ; in[1]                                                               ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[26]                                                                                                                                                  ;                              ; CLK0                         ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 41.891 ns                                      ; reg:inst12|q[13]                                                    ; P_10                                                                                                                                                                                                   ; CLK0                         ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 32.925 ns                                      ; in[1]                                                               ; P_10                                                                                                                                                                                                   ;                              ;                              ; 0            ;
; Clock Setup: 'CLK0'                         ; N/A   ; None          ; 44.01 MHz ( period = 22.720 ns )               ; reg:inst12|q[13]                                                    ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[26]                                                                                                                                                  ; CLK0                         ; CLK0                         ; 0            ;
; Clock Setup: 'STEP'                         ; N/A   ; None          ; 56.35 MHz ( period = 17.747 ns )               ; reg:inst12|q[13]                                                    ; control1:inst3|current_state~53                                                                                                                                                                        ; STEP                         ; STEP                         ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 124.77 MHz ( period = 8.015 ns )               ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1]                         ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[134] ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'P_11'                         ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; dsp:inst25|cnt4:212|lpm_counter:1|cntr_fa7:auto_generated|safe_q[1] ; dsp:inst25|cnt4:212|lpm_counter:1|cntr_fa7:auto_generated|safe_q[4]                                                                                                                                    ; P_11                         ; P_11                         ; 0            ;
; Total number of failed paths                ;       ;               ;                                                ;                                                                     ;                                                                                                                                                                                                        ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                            ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; STEP                         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; CLK0                         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; P_11                         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'STEP'                                                                                                                                                                                                                                                           ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                            ; To                              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 56.35 MHz ( period = 17.747 ns )                    ; reg:inst12|q[13]                ; control1:inst3|current_state~53 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 56.62 MHz ( period = 17.662 ns )                    ; reg:inst12|q[11]                ; control1:inst3|current_state~53 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 56.74 MHz ( period = 17.625 ns )                    ; reg:inst12|q[12]                ; control1:inst3|current_state~53 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 57.36 MHz ( period = 17.433 ns )                    ; reg:inst12|q[3]                 ; control1:inst3|current_state~53 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 57.67 MHz ( period = 17.339 ns )                    ; reg:inst12|q[15]                ; control1:inst3|current_state~53 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 57.72 MHz ( period = 17.326 ns )                    ; reg:inst12|q[4]                 ; control1:inst3|current_state~53 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 57.72 MHz ( period = 17.324 ns )                    ; reg:inst12|q[13]                ; control1:inst3|current_state~40 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 58.01 MHz ( period = 17.239 ns )                    ; reg:inst12|q[11]                ; control1:inst3|current_state~40 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 58.10 MHz ( period = 17.212 ns )                    ; reg:inst12|q[1]                 ; control1:inst3|current_state~53 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 58.13 MHz ( period = 17.202 ns )                    ; reg:inst12|q[12]                ; control1:inst3|current_state~40 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 58.54 MHz ( period = 17.081 ns )                    ; reg:inst12|q[14]                ; control1:inst3|current_state~53 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 58.62 MHz ( period = 17.059 ns )                    ; reg:inst12|q[0]                 ; control1:inst3|current_state~53 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;
; N/A                                     ; 58.79 MHz ( period = 17.010 ns )                    ; reg:inst12|q[3]                 ; control1:inst3|current_state~40 ; STEP       ; STEP     ; None                        ; None                      ; None                    ;