📄 control1.tan.rpt
字号:
+---------------+-------------+-----------+--------------+-----------------------+----------+
; N/A ; None ; -4.669 ns ; instrReg[13] ; current_state.move2 ; clock ;
; N/A ; None ; -4.762 ns ; instrReg[13] ; current_state.inc2 ; clock ;
; N/A ; None ; -4.765 ns ; instrReg[13] ; current_state.bgti2 ; clock ;
; N/A ; None ; -4.809 ns ; compout ; current_state.bgti5 ; clock ;
; N/A ; None ; -4.815 ns ; instrReg[13] ; current_state.load2 ; clock ;
; N/A ; None ; -4.890 ns ; instrReg[11] ; current_state.load2 ; clock ;
; N/A ; None ; -4.946 ns ; instrReg[13] ; current_state.store2 ; clock ;
; N/A ; None ; -4.985 ns ; instrReg[11] ; current_state.inc2 ; clock ;
; N/A ; None ; -4.985 ns ; instrReg[11] ; current_state.bgti2 ; clock ;
; N/A ; None ; -5.041 ns ; instrReg[12] ; current_state.load2 ; clock ;
; N/A ; None ; -5.063 ns ; compout ; current_state.incpc ; clock ;
; N/A ; None ; -5.155 ns ; ready ; current_state.reset6 ; clock ;
; N/A ; None ; -5.158 ns ; ready ; current_state.bgti10 ; clock ;
; N/A ; None ; -5.187 ns ; ready ; current_state.incpc6 ; clock ;
; N/A ; None ; -5.189 ns ; ready ; current_state.loadpc4 ; clock ;
; N/A ; None ; -5.196 ns ; instrReg[13] ; current_state.brai2 ; clock ;
; N/A ; None ; -5.198 ns ; instrReg[13] ; current_state.loadi2 ; clock ;
; N/A ; None ; -5.267 ns ; instrReg[11] ; current_state.move2 ; clock ;
; N/A ; None ; -5.326 ns ; instrReg[15] ; current_state.incpc ; clock ;
; N/A ; None ; -5.381 ns ; instrReg[11] ; current_state.store2 ; clock ;
; N/A ; None ; -5.393 ns ; ready ; current_state.loadi6 ; clock ;
; N/A ; None ; -5.646 ns ; instrReg[14] ; current_state.store2 ; clock ;
; N/A ; None ; -5.679 ns ; ready ; current_state.incpc ; clock ;
; N/A ; None ; -5.834 ns ; instrReg[15] ; current_state.load2 ; clock ;
; N/A ; None ; -5.850 ns ; instrReg[12] ; current_state.store2 ; clock ;
; N/A ; None ; -5.855 ns ; instrReg[15] ; current_state.store2 ; clock ;
; N/A ; None ; -5.871 ns ; instrReg[14] ; current_state.inc2 ; clock ;
; N/A ; None ; -5.871 ns ; instrReg[12] ; current_state.brai2 ; clock ;
; N/A ; None ; -5.872 ns ; instrReg[12] ; current_state.loadi2 ; clock ;
; N/A ; None ; -5.874 ns ; instrReg[14] ; current_state.bgti2 ; clock ;
; N/A ; None ; -5.884 ns ; instrReg[11] ; current_state.brai2 ; clock ;
; N/A ; None ; -5.888 ns ; instrReg[11] ; current_state.loadi2 ; clock ;
; N/A ; None ; -5.916 ns ; instrReg[15] ; current_state.brai2 ; clock ;
; N/A ; None ; -5.916 ns ; instrReg[15] ; current_state.loadi2 ; clock ;
; N/A ; None ; -6.075 ns ; instrReg[12] ; current_state.inc2 ; clock ;
; N/A ; None ; -6.078 ns ; instrReg[12] ; current_state.bgti2 ; clock ;
; N/A ; None ; -6.080 ns ; instrReg[15] ; current_state.inc2 ; clock ;
; N/A ; None ; -6.083 ns ; instrReg[15] ; current_state.bgti2 ; clock ;
; N/A ; None ; -6.109 ns ; instrReg[14] ; current_state.load2 ; clock ;
; N/A ; None ; -6.112 ns ; ready ; current_state.loadpc ; clock ;
; N/A ; None ; -6.115 ns ; ready ; current_state.brai6 ; clock ;
; N/A ; None ; -6.119 ns ; instrReg[14] ; current_state.move2 ; clock ;
; N/A ; None ; -6.191 ns ; instrReg[14] ; current_state.brai2 ; clock ;
; N/A ; None ; -6.191 ns ; instrReg[14] ; current_state.loadi2 ; clock ;
; N/A ; None ; -6.323 ns ; instrReg[12] ; current_state.move2 ; clock ;
; N/A ; None ; -6.328 ns ; instrReg[15] ; current_state.move2 ; clock ;
; N/A ; None ; -6.357 ns ; instrReg[13] ; current_state.incpc ; clock ;
; N/A ; None ; -6.423 ns ; instrReg[14] ; current_state.incpc ; clock ;
; N/A ; None ; -6.483 ns ; ready ; current_state.execute ; clock ;
; N/A ; None ; -6.712 ns ; instrReg[11] ; current_state.incpc ; clock ;
; N/A ; None ; -6.910 ns ; instrReg[12] ; current_state.incpc ; clock ;
+---------------+-------------+-----------+--------------+-----------------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.21 SJ Full Version
Info: Processing started: Tue Apr 25 16:55:08 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off control1 -c control1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 250.19 MHz between source register "current_state.inc4" and destination register "current_state.incpc" (period= 3.997 ns)
Info: + Longest register to register delay is 3.736 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y8_N2; Fanout = 2; REG Node = 'current_state.inc4'
Info: 2: + IC(0.528 ns) + CELL(0.590 ns) = 1.118 ns; Loc. = LC_X26_Y8_N3; Fanout = 2; COMB Node = 'reduce_or~307'
Info: 3: + IC(1.105 ns) + CELL(0.590 ns) = 2.813 ns; Loc. = LC_X26_Y8_N7; Fanout = 3; COMB Node = 'Select~893'
Info: 4: + IC(0.445 ns) + CELL(0.478 ns) = 3.736 ns; Loc. = LC_X26_Y8_N1; Fanout = 2; REG Node = 'current_state.incpc'
Info: Total cell delay = 1.658 ns ( 44.38 % )
Info: Total interconnect delay = 2.078 ns ( 55.62 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clock" to destination register is 2.910 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'
Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X26_Y8_N1; Fanout = 2; REG Node = 'current_state.incpc'
Info: Total cell delay = 2.180 ns ( 74.91 % )
Info: Total interconnect delay = 0.730 ns ( 25.09 % )
Info: - Longest clock path from clock "clock" to source register is 2.910 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'
Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X26_Y8_N2; Fanout = 2; REG Node = 'current_state.inc4'
Info: Total cell delay = 2.180 ns ( 74.91 % )
Info: Total interconnect delay = 0.730 ns ( 25.09 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "current_state.incpc" (data pin = "instrReg[12]", clock pin = "clock") is 6.962 ns
Info: + Longest pin to register delay is 9.835 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_138; Fanout = 9; PIN Node = 'instrReg[12]'
Info: 2: + IC(5.760 ns) + CELL(0.590 ns) = 7.819 ns; Loc. = LC_X28_Y8_N1; Fanout = 1; COMB Node = 'Mux~93'
Info: 3: + IC(1.083 ns) + CELL(0.442 ns) = 9.344 ns; Loc. = LC_X26_Y8_N0; Fanout = 1; COMB Node = 'next_state.incpc~34'
Info: 4: + IC(0.182 ns) + CELL(0.309 ns) = 9.835 ns; Loc. = LC_X26_Y8_N1; Fanout = 2; REG Node = 'current_state.incpc'
Info: Total cell delay = 2.810 ns ( 28.57 % )
Info: Total interconnect delay = 7.025 ns ( 71.43 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "clock" to destination register is 2.910 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'
Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X26_Y8_N1; Fanout = 2; REG Node = 'current_state.incpc'
Info: Total cell delay = 2.180 ns ( 74.91 % )
Info: Total interconnect delay = 0.730 ns ( 25.09 % )
Info: tco from clock "clock" to destination pin "aluSel[0]" through register "current_state.loadi2" is 13.358 ns
Info: + Longest clock path from clock "clock" to source register is 2.910 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'
Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X25_Y7_N6; Fanout = 2; REG Node = 'current_state.loadi2'
Info: Total cell delay = 2.180 ns ( 74.91 % )
Info: Total interconnect delay = 0.730 ns ( 25.09 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 10.224 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y7_N6; Fanout = 2; REG Node = 'current_state.loadi2'
Info: 2: + IC(1.161 ns) + CELL(0.590 ns) = 1.751 ns; Loc. = LC_X27_Y7_N4; Fanout = 2; COMB Node = 'Select~886'
Info: 3: + IC(1.133 ns) + CELL(0.292 ns) = 3.176 ns; Loc. = LC_X27_Y7_N9; Fanout = 2; COMB Node = 'Select~887'
Info: 4: + IC(1.261 ns) + CELL(0.114 ns) = 4.551 ns; Loc. = LC_X28_Y8_N7; Fanout = 3; COMB Node = 'Select~889'
Info: 5: + IC(1.552 ns) + CELL(0.292 ns) = 6.395 ns; Loc. = LC_X25_Y6_N4; Fanout = 1; COMB Node = 'Select~890'
Info: 6: + IC(1.721 ns) + CELL(2.108 ns) = 10.224 ns; Loc. = PIN_101; Fanout = 0; PIN Node = 'aluSel[0]'
Info: Total cell delay = 3.396 ns ( 33.22 % )
Info: Total interconnect delay = 6.828 ns ( 66.78 % )
Info: Longest tpd from source pin "instrReg[12]" to destination pin "regSel[1]" is 15.613 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_138; Fanout = 9; PIN Node = 'instrReg[12]'
Info: 2: + IC(5.761 ns) + CELL(0.590 ns) = 7.820 ns; Loc. = LC_X28_Y8_N0; Fanout = 1; COMB Node = 'Select~895'
Info: 3: + IC(0.427 ns) + CELL(0.114 ns) = 8.361 ns; Loc. = LC_X28_Y8_N2; Fanout = 1; COMB Node = 'Select~896'
Info: 4: + IC(1.577 ns) + CELL(0.292 ns) = 10.230 ns; Loc. = LC_X26_Y7_N4; Fanout = 3; COMB Node = 'Select~903'
Info: 5: + IC(1.584 ns) + CELL(0.292 ns) = 12.106 ns; Loc. = LC_X30_Y4_N5; Fanout = 1; COMB Node = 'Select~898'
Info: 6: + IC(1.399 ns) + CELL(2.108 ns) = 15.613 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'regSel[1]'
Info: Total cell delay = 4.865 ns ( 31.16 % )
Info: Total interconnect delay = 10.748 ns ( 68.84 % )
Info: th for register "current_state.move2" (data pin = "instrReg[13]", clock pin = "clock") is -4.669 ns
Info: + Longest clock path from clock "clock" to destination register is 2.910 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'
Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X27_Y8_N7; Fanout = 3; REG Node = 'current_state.move2'
Info: Total cell delay = 2.180 ns ( 74.91 % )
Info: Total interconnect delay = 0.730 ns ( 25.09 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 7.594 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_106; Fanout = 13; PIN Node = 'instrReg[13]'
Info: 2: + IC(5.641 ns) + CELL(0.478 ns) = 7.594 ns; Loc. = LC_X27_Y8_N7; Fanout = 3; REG Node = 'current_state.move2'
Info: Total cell delay = 1.953 ns ( 25.72 % )
Info: Total interconnect delay = 5.641 ns ( 74.28 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Tue Apr 25 16:55:10 2006
Info: Elapsed time: 00:00:02
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