top.hier_info

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

load => q[5]~reg0.ENA
load => q[4]~reg0.ENA
load => q[3]~reg0.ENA
load => q[2]~reg0.ENA
load => q[1]~reg0.ENA
load => q[0]~reg0.ENA
load => q[15]~reg0.ENA
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
d[8] => q[8]~reg0.DATAIN
d[9] => q[9]~reg0.DATAIN
d[10] => q[10]~reg0.DATAIN
d[11] => q[11]~reg0.DATAIN
d[12] => q[12]~reg0.DATAIN
d[13] => q[13]~reg0.DATAIN
d[14] => q[14]~reg0.DATAIN
d[15] => q[15]~reg0.DATAIN
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[10] <= q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[11] <= q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[12] <= q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[13] <= q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[14] <= q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[15] <= q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|top|lpm_bustri0:inst16
data[0] => lpm_bustri:lpm_bustri_component.data[0]
data[1] => lpm_bustri:lpm_bustri_component.data[1]
data[2] => lpm_bustri:lpm_bustri_component.data[2]
data[3] => lpm_bustri:lpm_bustri_component.data[3]
data[4] => lpm_bustri:lpm_bustri_component.data[4]
data[5] => lpm_bustri:lpm_bustri_component.data[5]
data[6] => lpm_bustri:lpm_bustri_component.data[6]
data[7] => lpm_bustri:lpm_bustri_component.data[7]
data[8] => lpm_bustri:lpm_bustri_component.data[8]
data[9] => lpm_bustri:lpm_bustri_component.data[9]
data[10] => lpm_bustri:lpm_bustri_component.data[10]
data[11] => lpm_bustri:lpm_bustri_component.data[11]
data[12] => lpm_bustri:lpm_bustri_component.data[12]
data[13] => lpm_bustri:lpm_bustri_component.data[13]
data[14] => lpm_bustri:lpm_bustri_component.data[14]
data[15] => lpm_bustri:lpm_bustri_component.data[15]
enabledt => lpm_bustri:lpm_bustri_component.enabledt
tridata[0] <= lpm_bustri:lpm_bustri_component.tridata[0]
tridata[1] <= lpm_bustri:lpm_bustri_component.tridata[1]
tridata[2] <= lpm_bustri:lpm_bustri_component.tridata[2]
tridata[3] <= lpm_bustri:lpm_bustri_component.tridata[3]
tridata[4] <= lpm_bustri:lpm_bustri_component.tridata[4]
tridata[5] <= lpm_bustri:lpm_bustri_component.tridata[5]
tridata[6] <= lpm_bustri:lpm_bustri_component.tridata[6]
tridata[7] <= lpm_bustri:lpm_bustri_component.tridata[7]
tridata[8] <= lpm_bustri:lpm_bustri_component.tridata[8]
tridata[9] <= lpm_bustri:lpm_bustri_component.tridata[9]
tridata[10] <= lpm_bustri:lpm_bustri_component.tridata[10]
tridata[11] <= lpm_bustri:lpm_bustri_component.tridata[11]
tridata[12] <= lpm_bustri:lpm_bustri_component.tridata[12]
tridata[13] <= lpm_bustri:lpm_bustri_component.tridata[13]
tridata[14] <= lpm_bustri:lpm_bustri_component.tridata[14]
tridata[15] <= lpm_bustri:lpm_bustri_component.tridata[15]


|top|lpm_bustri0:inst16|lpm_bustri:lpm_bustri_component
tridata[0] <= dout[0]
tridata[1] <= dout[1]
tridata[2] <= dout[2]
tridata[3] <= dout[3]
tridata[4] <= dout[4]
tridata[5] <= dout[5]
tridata[6] <= dout[6]
tridata[7] <= dout[7]
tridata[8] <= dout[8]
tridata[9] <= dout[9]
tridata[10] <= dout[10]
tridata[11] <= dout[11]
tridata[12] <= dout[12]
tridata[13] <= dout[13]
tridata[14] <= dout[14]
tridata[15] <= dout[15]
data[0] => dout[0].DATAIN
data[1] => dout[1].DATAIN
data[2] => dout[2].DATAIN
data[3] => dout[3].DATAIN
data[4] => dout[4].DATAIN
data[5] => dout[5].DATAIN
data[6] => dout[6].DATAIN
data[7] => dout[7].DATAIN
data[8] => dout[8].DATAIN
data[9] => dout[9].DATAIN
data[10] => dout[10].DATAIN
data[11] => dout[11].DATAIN
data[12] => dout[12].DATAIN
data[13] => dout[13].DATAIN
data[14] => dout[14].DATAIN
data[15] => dout[15].DATAIN
enabletr => ~NO_FANOUT~
enabledt => dout[15].OE
enabledt => dout[14].OE
enabledt => dout[13].OE
enabledt => dout[12].OE
enabledt => dout[11].OE
enabledt => dout[10].OE
enabledt => dout[9].OE
enabledt => dout[8].OE
enabledt => dout[7].OE
enabledt => dout[6].OE
enabledt => dout[5].OE
enabledt => dout[4].OE
enabledt => dout[3].OE
enabledt => dout[2].OE
enabledt => dout[1].OE
enabledt => dout[0].OE
result[0] <= tridata[0]~0.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= tridata[1]~1.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= tridata[2]~2.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= tridata[3]~3.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= tridata[4]~4.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= tridata[5]~5.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= tridata[6]~6.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= tridata[7]~7.DB_MAX_OUTPUT_PORT_TYPE
result[8] <= tridata[8]~8.DB_MAX_OUTPUT_PORT_TYPE
result[9] <= tridata[9]~9.DB_MAX_OUTPUT_PORT_TYPE
result[10] <= tridata[10]~10.DB_MAX_OUTPUT_PORT_TYPE
result[11] <= tridata[11]~11.DB_MAX_OUTPUT_PORT_TYPE
result[12] <= tridata[12]~12.DB_MAX_OUTPUT_PORT_TYPE
result[13] <= tridata[13]~13.DB_MAX_OUTPUT_PORT_TYPE
result[14] <= tridata[14]~14.DB_MAX_OUTPUT_PORT_TYPE
result[15] <= tridata[15]~15.DB_MAX_OUTPUT_PORT_TYPE


|top|ram_a:inst18
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
clock => altsyncram:altsyncram_component.clock0
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
data[8] => altsyncram:altsyncram_component.data_a[8]
data[9] => altsyncram:altsyncram_component.data_a[9]
data[10] => altsyncram:altsyncram_component.data_a[10]
data[11] => altsyncram:altsyncram_component.data_a[11]
data[12] => altsyncram:altsyncram_component.data_a[12]
data[13] => altsyncram:altsyncram_component.data_a[13]
data[14] => altsyncram:altsyncram_component.data_a[14]
data[15] => altsyncram:altsyncram_component.data_a[15]
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]
q[12] <= altsyncram:altsyncram_component.q_a[12]
q[13] <= altsyncram:altsyncram_component.q_a[13]
q[14] <= altsyncram:altsyncram_component.q_a[14]
q[15] <= altsyncram:altsyncram_component.q_a[15]


|top|ram_a:inst18|altsyncram:altsyncram_component
wren_a => altsyncram_5n21:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_5n21:auto_generated.data_a[0]
data_a[1] => altsyncram_5n21:auto_generated.data_a[1]
data_a[2] => altsyncram_5n21:auto_generated.data_a[2]
data_a[3] => altsyncram_5n21:auto_generated.data_a[3]
data_a[4] => altsyncram_5n21:auto_generated.data_a[4]
data_a[5] => altsyncram_5n21:auto_generated.data_a[5]
data_a[6] => altsyncram_5n21:auto_generated.data_a[6]
data_a[7] => altsyncram_5n21:auto_generated.data_a[7]
data_a[8] => altsyncram_5n21:auto_generated.data_a[8]
data_a[9] => altsyncram_5n21:auto_generated.data_a[9]
data_a[10] => altsyncram_5n21:auto_generated.data_a[10]
data_a[11] => altsyncram_5n21:auto_generated.data_a[11]
data_a[12] => altsyncram_5n21:auto_generated.data_a[12]
data_a[13] => altsyncram_5n21:auto_generated.data_a[13]
data_a[14] => altsyncram_5n21:auto_generated.data_a[14]
data_a[15] => altsyncram_5n21:auto_generated.data_a[15]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_5n21:auto_generated.address_a[0]
address_a[1] => altsyncram_5n21:auto_generated.address_a[1]
address_a[2] => altsyncram_5n21:auto_generated.address_a[2]
address_a[3] => altsyncram_5n21:auto_generated.address_a[3]
address_a[4] => altsyncram_5n21:auto_generated.address_a[4]
address_a[5] => altsyncram_5n21:auto_generated.address_a[5]
address_a[6] => altsyncram_5n21:auto_generated.address_a[6]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_5n21:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_5n21:auto_generated.q_a[0]
q_a[1] <= altsyncram_5n21:auto_generated.q_a[1]
q_a[2] <= altsyncram_5n21:auto_generated.q_a[2]
q_a[3] <= altsyncram_5n21:auto_generated.q_a[3]
q_a[4] <= altsyncram_5n21:auto_generated.q_a[4]
q_a[5] <= altsyncram_5n21:auto_generated.q_a[5]
q_a[6] <= altsyncram_5n21:auto_generated.q_a[6]
q_a[7] <= altsyncram_5n21:auto_generated.q_a[7]
q_a[8] <= altsyncram_5n21:auto_generated.q_a[8]
q_a[9] <= altsyncram_5n21:auto_generated.q_a[9]
q_a[10] <= altsyncram_5n21:auto_generated.q_a[10]
q_a[11] <= altsyncram_5n21:auto_generated.q_a[11]
q_a[12] <= altsyncram_5n21:auto_generated.q_a[12]
q_a[13] <= altsyncram_5n21:auto_generated.q_a[13]
q_a[14] <= altsyncram_5n21:auto_generated.q_a[14]
q_a[15] <= altsyncram_5n21:auto_generated.q_a[15]
q_b[0] <= <UNC>


|top|ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated
address_a[0] => altsyncram_7gd2:altsyncram1.address_a[0]
address_a[1] => altsyncram_7gd2:altsyncram1.address_a[1]
address_a[2] => altsyncram_7gd2:altsyncram1.address_a[2]
address_a[3] => altsyncram_7gd2:altsyncram1.address_a[3]
address_a[4] => altsyncram_7gd2:altsyncram1.address_a[4]
address_a[5] => altsyncram_7gd2:altsyncram1.address_a[5]
address_a[6] => altsyncram_7gd2:altsyncram1.address_a[6]
clock0 => altsyncram_7gd2:altsyncram1.clock0
data_a[0] => altsyncram_7gd2:altsyncram1.data_a[0]
data_a[1] => altsyncram_7gd2:altsyncram1.data_a[1]
data_a[2] => altsyncram_7gd2:altsyncram1.data_a[2]
data_a[3] => altsyncram_7gd2:altsyncram1.data_a[3]
data_a[4] => altsyncram_7gd2:altsyncram1.data_a[4]
data_a[5] => altsyncram_7gd2:altsyncram1.data_a[5]
data_a[6] => altsyncram_7gd2:altsyncram1.data_a[6]
data_a[7] => altsyncram_7gd2:altsyncram1.data_a[7]
data_a[8] => altsyncram_7gd2:altsyncram1.data_a[8]
data_a[9] => altsyncram_7gd2:altsyncram1.data_a[9]
data_a[10] => altsyncram_7gd2:altsyncram1.data_a[10]
data_a[11] => altsyncram_7gd2:altsyncram1.data_a[11]
data_a[12] => altsyncram_7gd2:altsyncram1.data_a[12]
data_a[13] => altsyncram_7gd2:altsyncram1.data_a[13]
data_a[14] => altsyncram_7gd2:altsyncram1.data_a[14]
data_a[15] => altsyncram_7gd2:altsyncram1.data_a[15]
q_a[0] <= altsyncram_7gd2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_7gd2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_7gd2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_7gd2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_7gd2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_7gd2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_7gd2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_7gd2:altsyncram1.q_a[7]
q_a[8] <= altsyncram_7gd2:altsyncram1.q_a[8]
q_a[9] <= altsyncram_7gd2:altsyncram1.q_a[9]
q_a[10] <= altsyncram_7gd2:altsyncram1.q_a[10]
q_a[11] <= altsyncram_7gd2:altsyncram1.q_a[11]
q_a[12] <= altsyncram_7gd2:altsyncram1.q_a[12]
q_a[13] <= altsyncram_7gd2:altsyncram1.q_a[13]
q_a[14] <= altsyncram_7gd2:altsyncram1.q_a[14]
q_a[15] <= altsyncram_7gd2:altsyncram1.q_a[15]
wren_a => altsyncram_7gd2:altsyncram1.wren_a


|top|ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[0] => ram_block3a8.PORTAADDR
address_a[0] => ram_block3a9.PORTAADDR
address_a[0] => ram_block3a10.PORTAADDR
address_a[0] => ram_block3a11.PORTAADDR
address_a[0] => ram_block3a12.PORTAADDR
address_a[0] => ram_block3a13.PORTAADDR
address_a[0] => ram_block3a14.PORTAADDR
address_a[0] => ram_block3a15.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[1] => ram_block3a8.PORTAADDR1
address_a[1] => ram_block3a9.PORTAADDR1
address_a[1] => ram_block3a10.PORTAADDR1
address_a[1] => ram_block3a11.PORTAADDR1
address_a[1] => ram_block3a12.PORTAADDR1
address_a[1] => ram_block3a13.PORTAADDR1
address_a[1] => ram_block3a14.PORTAADDR1
address_a[1] => ram_block3a15.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[2] => ram_block3a8.PORTAADDR2
address_a[2] => ram_block3a9.PORTAADDR2
address_a[2] => ram_block3a10.PORTAADDR2
address_a[2] => ram_block3a11.PORTAADDR2
address_a[2] => ram_block3a12.PORTAADDR2
address_a[2] => ram_block3a13.PORTAADDR2
address_a[2] => ram_block3a14.PORTAADDR2
address_a[2] => ram_block3a15.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[3] => ram_block3a8.PORTAADDR3
address_a[3] => ram_block3a9.PORTAADDR3
address_a[3] => ram_block3a10.PORTAADDR3
address_a[3] => ram_block3a11.PORTAADDR3
address_a[3] => ram_block3a12.PORTAADDR3
address_a[3] => ram_block3a13.PORTAADDR3
address_a[3] => ram_block3a14.PORTAADDR3
address_a[3] => ram_block3a15.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[4] => ram_block3a8.PORTAADDR4
address_a[4] => ram_block3a9.PORTAADDR4
address_a[4] => ram_block3a10.PORTAADDR4
address_a[4] => ram_block3a11.PORTAADDR4
address_a[4] => ram_block3a12.PORTAADDR4
address_a[4] => ram_block3a13.PORTAADDR4
address_a[4] => ram_block3a14.PORTAADDR4
address_a[4] => ram_block3a15.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[5] => ram_block3a8.PORTAADDR5
address_a[5] => ram_block3a9.PORTAADDR5
address_a[5] => ram_block3a10.PORTAADDR5
address_a[5] => ram_block3a11.PORTAADDR5
address_a[5] => ram_block3a12.PORTAADDR5
address_a[5] => ram_block3a13.PORTAADDR5
address_a[5] => ram_block3a14.PORTAADDR5
address_a[5] => ram_block3a15.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[6] => ram_block3a8.PORTAADDR6
address_a[6] => ram_block3a9.PORTAADDR6
address_a[6] => ram_block3a10.PORTAADDR6
address_a[6] => ram_block3a11.PORTAADDR6
address_a[6] => ram_block3a12.PORTAADDR6
address_a[6] => ram_block3a13.PORTAADDR6
address_a[6] => ram_block3a14.PORTAADDR6
address_a[6] => ram_block3a15.PORTAADDR6
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[0] => ram_block3a8.PORTBADDR
address_b[0] => ram_block3a9.PORTBADDR
address_b[0] => ram_block3a10.PORTBADDR
address_b[0] => ram_block3a11.PORTBADDR
address_b[0] => ram_block3a12.PORTBADDR
address_b[0] => ram_block3a13.PORTBADDR
address_b[0] => ram_block3a14.PORTBADDR
address_b[0] => ram_block3a15.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a