top.hier_info

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

b[3] => LessThan~3.IN29
b[4] => nequal~4.IN1
b[4] => LessThan~0.IN28
b[4] => LessThan~1.IN28
b[4] => LessThan~2.IN28
b[4] => LessThan~3.IN28
b[5] => nequal~5.IN1
b[5] => LessThan~0.IN27
b[5] => LessThan~1.IN27
b[5] => LessThan~2.IN27
b[5] => LessThan~3.IN27
b[6] => nequal~6.IN1
b[6] => LessThan~0.IN26
b[6] => LessThan~1.IN26
b[6] => LessThan~2.IN26
b[6] => LessThan~3.IN26
b[7] => nequal~7.IN1
b[7] => LessThan~0.IN25
b[7] => LessThan~1.IN25
b[7] => LessThan~2.IN25
b[7] => LessThan~3.IN25
b[8] => nequal~8.IN1
b[8] => LessThan~0.IN24
b[8] => LessThan~1.IN24
b[8] => LessThan~2.IN24
b[8] => LessThan~3.IN24
b[9] => nequal~9.IN1
b[9] => LessThan~0.IN23
b[9] => LessThan~1.IN23
b[9] => LessThan~2.IN23
b[9] => LessThan~3.IN23
b[10] => nequal~10.IN1
b[10] => LessThan~0.IN22
b[10] => LessThan~1.IN22
b[10] => LessThan~2.IN22
b[10] => LessThan~3.IN22
b[11] => nequal~11.IN1
b[11] => LessThan~0.IN21
b[11] => LessThan~1.IN21
b[11] => LessThan~2.IN21
b[11] => LessThan~3.IN21
b[12] => nequal~12.IN1
b[12] => LessThan~0.IN20
b[12] => LessThan~1.IN20
b[12] => LessThan~2.IN20
b[12] => LessThan~3.IN20
b[13] => nequal~13.IN1
b[13] => LessThan~0.IN19
b[13] => LessThan~1.IN19
b[13] => LessThan~2.IN19
b[13] => LessThan~3.IN19
b[14] => nequal~14.IN1
b[14] => LessThan~0.IN18
b[14] => LessThan~1.IN18
b[14] => LessThan~2.IN18
b[14] => LessThan~3.IN18
b[15] => nequal~15.IN1
b[15] => LessThan~0.IN17
b[15] => LessThan~1.IN17
b[15] => LessThan~2.IN17
b[15] => LessThan~3.IN17
sel[0] => Mux~0.IN4
sel[1] => Mux~0.IN3
sel[2] => Mux~0.IN2
compout <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE


|top|reg_l:inst21
rst => q[14]~reg0.ACLR
rst => q[13]~reg0.ACLR
rst => q[12]~reg0.ACLR
rst => q[11]~reg0.ACLR
rst => q[10]~reg0.ACLR
rst => q[9]~reg0.ACLR
rst => q[8]~reg0.ACLR
rst => q[7]~reg0.ACLR
rst => q[6]~reg0.ACLR
rst => q[5]~reg0.ACLR
rst => q[4]~reg0.ACLR
rst => q[3]~reg0.ACLR
rst => q[2]~reg0.ACLR
rst => q[1]~reg0.ACLR
rst => q[0]~reg0.ACLR
rst => q[15]~reg0.ACLR
clk => q[14]~reg0.CLK
clk => q[13]~reg0.CLK
clk => q[12]~reg0.CLK
clk => q[11]~reg0.CLK
clk => q[10]~reg0.CLK
clk => q[9]~reg0.CLK
clk => q[8]~reg0.CLK
clk => q[7]~reg0.CLK
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[15]~reg0.CLK
load => q[14]~reg0.ENA
load => q[13]~reg0.ENA
load => q[12]~reg0.ENA
load => q[11]~reg0.ENA
load => q[10]~reg0.ENA
load => q[9]~reg0.ENA
load => q[8]~reg0.ENA
load => q[7]~reg0.ENA
load => q[6]~reg0.ENA
load => q[5]~reg0.ENA
load => q[4]~reg0.ENA
load => q[3]~reg0.ENA
load => q[2]~reg0.ENA
load => q[1]~reg0.ENA
load => q[0]~reg0.ENA
load => q[15]~reg0.ENA
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
d[8] => q[8]~reg0.DATAIN
d[9] => q[9]~reg0.DATAIN
d[10] => q[10]~reg0.DATAIN
d[11] => q[11]~reg0.DATAIN
d[12] => q[12]~reg0.DATAIN
d[13] => q[13]~reg0.DATAIN
d[14] => q[14]~reg0.DATAIN
d[15] => q[15]~reg0.DATAIN
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[10] <= q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[11] <= q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[12] <= q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[13] <= q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[14] <= q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[15] <= q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|top|STEP9:inst2
RESET => RESET~I.PADIO
CLK => CLK~I.PADIO
STEP => STEP~I.PADIO
NESW => NESW~I.PADIO
DOUT <= DOUT~I.PADIO
XX0 <= XX0~I.PADIO
XX1 <= XX1~I.PADIO
XX2 <= XX2~I.PADIO
T1 <= T1~I.PADIO
T2 <= T2~I.PADIO
T3 <= T3~I.PADIO
T4 <= T4~I.PADIO
POE[0] <= POE[0]~I.PADIO
POE[1] <= POE[1]~I.PADIO
POE[2] <= POE[2]~I.PADIO
POE[3] <= POE[3]~I.PADIO
POE[4] <= POE[4]~I.PADIO
POE[5] <= POE[5]~I.PADIO
POE[6] <= POE[6]~I.PADIO
POE[7] <= POE[7]~I.PADIO


|top|trireg:inst7
a[0] => val[0].DATAIN
a[1] => val[1].DATAIN
a[2] => val[2].DATAIN
a[3] => val[3].DATAIN
a[4] => val[4].DATAIN
a[5] => val[5].DATAIN
a[6] => val[6].DATAIN
a[7] => val[7].DATAIN
a[8] => val[8].DATAIN
a[9] => val[9].DATAIN
a[10] => val[10].DATAIN
a[11] => val[11].DATAIN
a[12] => val[12].DATAIN
a[13] => val[13].DATAIN
a[14] => val[14].DATAIN
a[15] => val[15].DATAIN
en => trireg3st~1.OE
en => trireg3st~3.OE
en => trireg3st~5.OE
en => trireg3st~7.OE
en => trireg3st~9.OE
en => trireg3st~11.OE
en => trireg3st~13.OE
en => trireg3st~15.OE
en => trireg3st~17.OE
en => trireg3st~19.OE
en => trireg3st~21.OE
en => trireg3st~23.OE
en => trireg3st~25.OE
en => trireg3st~27.OE
en => trireg3st~29.OE
en => trireg3st~31.OE
clk => val[14].CLK
clk => val[13].CLK
clk => val[12].CLK
clk => val[11].CLK
clk => val[10].CLK
clk => val[9].CLK
clk => val[8].CLK
clk => val[7].CLK
clk => val[6].CLK
clk => val[5].CLK
clk => val[4].CLK
clk => val[3].CLK
clk => val[2].CLK
clk => val[1].CLK
clk => val[0].CLK
clk => val[15].CLK
q[0] <= trireg3st~31.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= trireg3st~29.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= trireg3st~27.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= trireg3st~25.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= trireg3st~23.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= trireg3st~21.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= trireg3st~19.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= trireg3st~17.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= trireg3st~15.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= trireg3st~13.DB_MAX_OUTPUT_PORT_TYPE
q[10] <= trireg3st~11.DB_MAX_OUTPUT_PORT_TYPE
q[11] <= trireg3st~9.DB_MAX_OUTPUT_PORT_TYPE
q[12] <= trireg3st~7.DB_MAX_OUTPUT_PORT_TYPE
q[13] <= trireg3st~5.DB_MAX_OUTPUT_PORT_TYPE
q[14] <= trireg3st~3.DB_MAX_OUTPUT_PORT_TYPE
q[15] <= trireg3st~1.DB_MAX_OUTPUT_PORT_TYPE


|top|shift:inst5
a[0] => Mux~0.IN7
a[0] => Mux~14.IN6
a[0] => Mux~14.IN7
a[0] => Mux~15.IN7
a[1] => Mux~13.IN6
a[1] => Mux~13.IN7
a[1] => Mux~14.IN5
a[1] => Mux~15.IN5
a[1] => Mux~15.IN6
a[2] => Mux~12.IN6
a[2] => Mux~12.IN7
a[2] => Mux~13.IN5
a[2] => Mux~14.IN3
a[2] => Mux~14.IN4
a[3] => Mux~11.IN6
a[3] => Mux~11.IN7
a[3] => Mux~12.IN5
a[3] => Mux~13.IN3
a[3] => Mux~13.IN4
a[4] => Mux~10.IN6
a[4] => Mux~10.IN7
a[4] => Mux~11.IN5
a[4] => Mux~12.IN3
a[4] => Mux~12.IN4
a[5] => Mux~9.IN6
a[5] => Mux~9.IN7
a[5] => Mux~10.IN5
a[5] => Mux~11.IN3
a[5] => Mux~11.IN4
a[6] => Mux~8.IN6
a[6] => Mux~8.IN7
a[6] => Mux~9.IN5
a[6] => Mux~10.IN3
a[6] => Mux~10.IN4
a[7] => Mux~7.IN6
a[7] => Mux~7.IN7
a[7] => Mux~8.IN5
a[7] => Mux~9.IN3
a[7] => Mux~9.IN4
a[8] => Mux~6.IN6
a[8] => Mux~6.IN7
a[8] => Mux~7.IN5
a[8] => Mux~8.IN3
a[8] => Mux~8.IN4
a[9] => Mux~5.IN6
a[9] => Mux~5.IN7
a[9] => Mux~6.IN5
a[9] => Mux~7.IN3
a[9] => Mux~7.IN4
a[10] => Mux~4.IN6
a[10] => Mux~4.IN7
a[10] => Mux~5.IN5
a[10] => Mux~6.IN3
a[10] => Mux~6.IN4
a[11] => Mux~3.IN6
a[11] => Mux~3.IN7
a[11] => Mux~4.IN5
a[11] => Mux~5.IN3
a[11] => Mux~5.IN4
a[12] => Mux~2.IN6
a[12] => Mux~2.IN7
a[12] => Mux~3.IN5
a[12] => Mux~4.IN3
a[12] => Mux~4.IN4
a[13] => Mux~1.IN6
a[13] => Mux~1.IN7
a[13] => Mux~2.IN5
a[13] => Mux~3.IN3
a[13] => Mux~3.IN4
a[14] => Mux~0.IN5
a[14] => Mux~0.IN6
a[14] => Mux~1.IN5
a[14] => Mux~2.IN3
a[14] => Mux~2.IN4
a[15] => Mux~0.IN4
a[15] => Mux~1.IN3
a[15] => Mux~1.IN4
a[15] => Mux~15.IN4
sel[0] => Mux~0.IN10
sel[0] => Mux~1.IN10
sel[0] => Mux~2.IN10
sel[0] => Mux~3.IN10
sel[0] => Mux~4.IN10
sel[0] => Mux~5.IN10
sel[0] => Mux~6.IN10
sel[0] => Mux~7.IN10
sel[0] => Mux~8.IN10
sel[0] => Mux~9.IN10
sel[0] => Mux~10.IN10
sel[0] => Mux~11.IN10
sel[0] => Mux~12.IN10
sel[0] => Mux~13.IN10
sel[0] => Mux~14.IN10
sel[0] => Mux~15.IN10
sel[1] => Mux~0.IN9
sel[1] => Mux~1.IN9
sel[1] => Mux~2.IN9
sel[1] => Mux~3.IN9
sel[1] => Mux~4.IN9
sel[1] => Mux~5.IN9
sel[1] => Mux~6.IN9
sel[1] => Mux~7.IN9
sel[1] => Mux~8.IN9
sel[1] => Mux~9.IN9
sel[1] => Mux~10.IN9
sel[1] => Mux~11.IN9
sel[1] => Mux~12.IN9
sel[1] => Mux~13.IN9
sel[1] => Mux~14.IN9
sel[1] => Mux~15.IN9
sel[2] => Mux~0.IN8
sel[2] => Mux~1.IN8
sel[2] => Mux~2.IN8
sel[2] => Mux~3.IN8
sel[2] => Mux~4.IN8
sel[2] => Mux~5.IN8
sel[2] => Mux~6.IN8
sel[2] => Mux~7.IN8
sel[2] => Mux~8.IN8
sel[2] => Mux~9.IN8
sel[2] => Mux~10.IN8
sel[2] => Mux~11.IN8
sel[2] => Mux~12.IN8
sel[2] => Mux~13.IN8
sel[2] => Mux~14.IN8
sel[2] => Mux~15.IN8
y[0] <= Mux~15.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= Mux~14.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= Mux~13.DB_MAX_OUTPUT_PORT_TYPE
y[3] <= Mux~12.DB_MAX_OUTPUT_PORT_TYPE
y[4] <= Mux~11.DB_MAX_OUTPUT_PORT_TYPE
y[5] <= Mux~10.DB_MAX_OUTPUT_PORT_TYPE
y[6] <= Mux~9.DB_MAX_OUTPUT_PORT_TYPE
y[7] <= Mux~8.DB_MAX_OUTPUT_PORT_TYPE
y[8] <= Mux~7.DB_MAX_OUTPUT_PORT_TYPE
y[9] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
y[10] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
y[11] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
y[12] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
y[13] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
y[14] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
y[15] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE


|top|alu:inst
a[0] => c~0.IN0
a[0] => c~16.IN0
a[0] => c~32.IN0
a[0] => add~0.IN16
a[0] => add~1.IN16
a[0] => add~2.IN32
a[0] => add~3.IN32
a[0] => Mux~15.IN7
a[0] => Mux~15.IN15
a[1] => c~1.IN0
a[1] => c~17.IN0
a[1] => c~33.IN0
a[1] => add~0.IN15
a[1] => add~1.IN15
a[1] => add~2.IN31
a[1] => add~3.IN31
a[1] => Mux~14.IN7
a[1] => Mux~14.IN15
a[2] => c~2.IN0
a[2] => c~18.IN0
a[2] => c~34.IN0
a[2] => add~0.IN14
a[2] => add~1.IN14
a[2] => add~2.IN30
a[2] => add~3.IN30
a[2] => Mux~13.IN7
a[2] => Mux~13.IN15
a[3] => c~3.IN0
a[3] => c~19.IN0
a[3] => c~35.IN0
a[3] => add~0.IN13
a[3] => add~1.IN13
a[3] => add~2.IN29
a[3] => add~3.IN29
a[3] => Mux~12.IN7
a[3] => Mux~12.IN15
a[4] => c~4.IN0
a[4] => c~20.IN0
a[4] => c~36.IN0
a[4] => add~0.IN12
a[4] => add~1.IN12
a[4] => add~2.IN28