top.hier_info

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

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regRD <= control1:inst3.regRd
STEP => control1:inst3.clock
STEP => STEP9:inst2.STEP
RST => control1:inst3.reset
RST => reg_l:inst21.rst
RST => STEP9:inst2.RESET
RST => reg_l:inst17.rst
RST => reg_l:inst13.rst
T1 <= STEP9:inst2.T1
CLK0 => STEP9:inst2.CLK
NESW => STEP9:inst2.NESW
T2 <= STEP9:inst2.T2
reg_q[0] <= regarray:inst10.q[0]
reg_q[1] <= regarray:inst10.q[1]
reg_q[2] <= regarray:inst10.q[2]
reg_q[3] <= regarray:inst10.q[3]
reg_q[4] <= regarray:inst10.q[4]
reg_q[5] <= regarray:inst10.q[5]
reg_q[6] <= regarray:inst10.q[6]
reg_q[7] <= regarray:inst10.q[7]
pc[0] <= reg_l:inst17.q[0]
pc[1] <= reg_l:inst17.q[1]
pc[2] <= reg_l:inst17.q[2]
pc[3] <= reg_l:inst17.q[3]
pc[4] <= reg_l:inst17.q[4]
pc[5] <= reg_l:inst17.q[5]
pc[6] <= reg_l:inst17.q[6]
pc[7] <= reg_l:inst17.q[7]
addr[0] <= reg_l:inst13.q[0]
addr[1] <= reg_l:inst13.q[1]
addr[2] <= reg_l:inst13.q[2]
addr[3] <= reg_l:inst13.q[3]
addr[4] <= reg_l:inst13.q[4]
addr[5] <= reg_l:inst13.q[5]
addr[6] <= reg_l:inst13.q[6]
addr[7] <= reg_l:inst13.q[7]
in[0] => lpm_bustri0:inst15.data[0]
in[0] => dsp:inst25.P[1][0]
in[1] => lpm_bustri0:inst15.data[1]
in[1] => dsp:inst25.P[1][1]
in[2] => lpm_bustri0:inst15.data[2]
in[2] => dsp:inst25.P[1][2]
in[3] => lpm_bustri0:inst15.data[3]
in[3] => dsp:inst25.P[1][3]
in[4] => lpm_bustri0:inst15.data[4]
in[4] => dsp:inst25.P[1][4]
in[5] => lpm_bustri0:inst15.data[5]
in[5] => dsp:inst25.P[1][5]
in[6] => lpm_bustri0:inst15.data[6]
in[6] => dsp:inst25.P[1][6]
in[7] => lpm_bustri0:inst15.data[7]
in[7] => dsp:inst25.P[1][7]
in[8] => lpm_bustri0:inst15.data[8]
in[8] => dsp:inst25.P[0][0]
in[9] => lpm_bustri0:inst15.data[9]
in[9] => dsp:inst25.P[0][1]
in[10] => lpm_bustri0:inst15.data[10]
in[10] => dsp:inst25.P[0][2]
in[11] => lpm_bustri0:inst15.data[11]
in[11] => dsp:inst25.P[0][3]
in[12] => lpm_bustri0:inst15.data[12]
in[12] => dsp:inst25.P[0][4]
in[13] => lpm_bustri0:inst15.data[13]
in[13] => dsp:inst25.P[0][5]
in[14] => lpm_bustri0:inst15.data[14]
in[14] => dsp:inst25.P[0][6]
in[15] => lpm_bustri0:inst15.data[15]
in[15] => dsp:inst25.P[0][7]
b[0] <= reg_l:inst21.q[0]
b[1] <= reg_l:inst21.q[1]
b[2] <= reg_l:inst21.q[2]
b[3] <= reg_l:inst21.q[3]
b[4] <= reg_l:inst21.q[4]
b[5] <= reg_l:inst21.q[5]
b[6] <= reg_l:inst21.q[6]
b[7] <= reg_l:inst21.q[7]
regWr <= control1:inst3.regWr
rw <= control1:inst3.rw
opRegWr <= control1:inst3.opRegWr
opRegRd <= control1:inst3.opRegRd
outRegRd <= control1:inst3.outRegRd
outRegWr <= control1:inst3.outRegWr
progCntrWr <= control1:inst3.progCntrWr
progCntrRd <= control1:inst3.progCntrRd
addrRegWr <= control1:inst3.addrRegWr
instrWr <= control1:inst3.instrWr
cmpout <= comp:inst1.compout
P_10 <= dsp:inst25.P10
P_11 => dsp:inst25.P11
P_12 => dsp:inst25.P12
out[0] <= reg:inst24.q[0]
out[1] <= reg:inst24.q[1]
out[2] <= reg:inst24.q[2]
out[3] <= reg:inst24.q[3]
out[4] <= reg:inst24.q[4]
out[5] <= reg:inst24.q[5]
out[6] <= reg:inst24.q[6]
out[7] <= reg:inst24.q[7]
out[8] <= reg:inst24.q[8]
out[9] <= reg:inst24.q[9]
out[10] <= reg:inst24.q[10]
out[11] <= reg:inst24.q[11]
out[12] <= reg:inst24.q[12]
out[13] <= reg:inst24.q[13]
out[14] <= reg:inst24.q[14]
out[15] <= reg:inst24.q[15]
alu[0] <= alu:inst.c[0]
alu[1] <= alu:inst.c[1]
alu[2] <= alu:inst.c[2]
alu[3] <= alu:inst.c[3]
alu[4] <= alu:inst.c[4]
alu[5] <= alu:inst.c[5]
alu[6] <= alu:inst.c[6]
alu[7] <= alu:inst.c[7]
alu[8] <= alu:inst.c[8]
alu[9] <= alu:inst.c[9]
alu[10] <= alu:inst.c[10]
alu[11] <= alu:inst.c[11]
alu[12] <= alu:inst.c[12]
alu[13] <= alu:inst.c[13]
alu[14] <= alu:inst.c[14]
alu[15] <= alu:inst.c[15]
BUS[0] <= gdfx_temp0[0].DB_MAX_OUTPUT_PORT_TYPE
BUS[1] <= gdfx_temp0[1].DB_MAX_OUTPUT_PORT_TYPE
BUS[2] <= gdfx_temp0[2].DB_MAX_OUTPUT_PORT_TYPE
BUS[3] <= gdfx_temp0[3].DB_MAX_OUTPUT_PORT_TYPE
BUS[4] <= gdfx_temp0[4].DB_MAX_OUTPUT_PORT_TYPE
BUS[5] <= gdfx_temp0[5].DB_MAX_OUTPUT_PORT_TYPE
BUS[6] <= gdfx_temp0[6].DB_MAX_OUTPUT_PORT_TYPE
BUS[7] <= gdfx_temp0[7].DB_MAX_OUTPUT_PORT_TYPE
BUS[8] <= gdfx_temp0[8].DB_MAX_OUTPUT_PORT_TYPE
BUS[9] <= gdfx_temp0[9].DB_MAX_OUTPUT_PORT_TYPE
BUS[10] <= gdfx_temp0[10].DB_MAX_OUTPUT_PORT_TYPE
BUS[11] <= gdfx_temp0[11].DB_MAX_OUTPUT_PORT_TYPE
BUS[12] <= gdfx_temp0[12].DB_MAX_OUTPUT_PORT_TYPE
BUS[13] <= gdfx_temp0[13].DB_MAX_OUTPUT_PORT_TYPE
BUS[14] <= gdfx_temp0[14].DB_MAX_OUTPUT_PORT_TYPE
BUS[15] <= gdfx_temp0[15].DB_MAX_OUTPUT_PORT_TYPE
instr[0] <= reg:inst12.q[0]
instr[1] <= reg:inst12.q[1]
instr[2] <= reg:inst12.q[2]
instr[3] <= reg:inst12.q[3]
instr[4] <= reg:inst12.q[4]
instr[5] <= reg:inst12.q[5]
instr[6] <= reg:inst12.q[6]
instr[7] <= reg:inst12.q[7]
instr[8] <= reg:inst12.q[8]
instr[9] <= reg:inst12.q[9]
instr[10] <= reg:inst12.q[10]
instr[11] <= reg:inst12.q[11]
instr[12] <= reg:inst12.q[12]
instr[13] <= reg:inst12.q[13]
instr[14] <= reg:inst12.q[14]
instr[15] <= reg:inst12.q[15]
p35 <= STEP9:inst2.XX2
p36 <= STEP9:inst2.XX0
p37 <= STEP9:inst2.XX1
alusel[0] <= control1:inst3.aluSel[0]
alusel[1] <= control1:inst3.aluSel[1]
alusel[2] <= control1:inst3.aluSel[2]
alusel[3] <= control1:inst3.aluSel[3]
cmpsel[0] <= control1:inst3.compSel[0]
cmpsel[1] <= control1:inst3.compSel[1]
cmpsel[2] <= control1:inst3.compSel[2]
POE[0] <= STEP9:inst2.POE[0]
POE[1] <= STEP9:inst2.POE[1]
POE[2] <= STEP9:inst2.POE[2]
POE[3] <= STEP9:inst2.POE[3]
POE[4] <= STEP9:inst2.POE[4]
POE[5] <= STEP9:inst2.POE[5]
reg[0] <= control1:inst3.regSel[0]
reg[1] <= control1:inst3.regSel[1]
reg[2] <= control1:inst3.regSel[2]
sftsel[0] <= control1:inst3.shiftSel[0]
sftsel[1] <= control1:inst3.shiftSel[1]
sftsel[2] <= control1:inst3.shiftSel[2]


|top|control1:inst3
clock => current_state~0.IN1
reset => current_state~1.IN1
instrReg[0] => Mux~10.IN35
instrReg[0] => Mux~10.IN36
instrReg[0] => regSel~2.DATAB
instrReg[0] => Select~5.IN2
instrReg[1] => Mux~9.IN35
instrReg[1] => Mux~9.IN36
instrReg[1] => regSel~1.DATAB
instrReg[1] => Select~4.IN2
instrReg[2] => Mux~8.IN35
instrReg[2] => Mux~8.IN36
instrReg[2] => regSel~0.DATAB
instrReg[2] => Select~3.IN2
instrReg[3] => Mux~10.IN32
instrReg[3] => Mux~10.IN33
instrReg[3] => Mux~10.IN34
instrReg[3] => Select~5.IN1
instrReg[4] => Mux~9.IN32
instrReg[4] => Mux~9.IN33
instrReg[4] => Mux~9.IN34
instrReg[4] => Select~4.IN1
instrReg[5] => Mux~8.IN32
instrReg[5] => Mux~8.IN33
instrReg[5] => Mux~8.IN34
instrReg[5] => Select~3.IN1
instrReg[6] => ~NO_FANOUT~
instrReg[7] => ~NO_FANOUT~
instrReg[8] => ~NO_FANOUT~
instrReg[9] => ~NO_FANOUT~
instrReg[10] => ~NO_FANOUT~
instrReg[11] => Mux~0.IN36
instrReg[11] => Mux~1.IN36
instrReg[11] => Mux~2.IN36
instrReg[11] => Mux~3.IN36
instrReg[11] => Mux~4.IN36
instrReg[11] => Mux~5.IN36
instrReg[11] => Mux~6.IN36
instrReg[11] => Mux~7.IN36
instrReg[11] => Mux~8.IN31
instrReg[11] => Mux~9.IN31
instrReg[11] => Mux~10.IN31
instrReg[11] => Mux~11.IN36
instrReg[11] => Mux~12.IN36
instrReg[12] => Mux~0.IN35
instrReg[12] => Mux~1.IN35
instrReg[12] => Mux~2.IN35
instrReg[12] => Mux~3.IN35
instrReg[12] => Mux~4.IN35
instrReg[12] => Mux~5.IN35
instrReg[12] => Mux~6.IN35
instrReg[12] => Mux~7.IN35
instrReg[12] => Mux~8.IN30
instrReg[12] => Mux~9.IN30
instrReg[12] => Mux~10.IN30
instrReg[12] => Mux~11.IN35
instrReg[12] => Mux~12.IN35
instrReg[12] => Mux~13.IN19
instrReg[13] => Mux~0.IN34
instrReg[13] => Mux~1.IN34
instrReg[13] => Mux~2.IN34
instrReg[13] => Mux~3.IN34
instrReg[13] => Mux~4.IN34
instrReg[13] => Mux~5.IN34
instrReg[13] => Mux~6.IN34
instrReg[13] => Mux~7.IN34
instrReg[13] => Mux~8.IN29
instrReg[13] => Mux~9.IN29
instrReg[13] => Mux~10.IN29
instrReg[13] => Mux~11.IN34
instrReg[13] => Mux~12.IN34
instrReg[13] => Mux~13.IN18
instrReg[14] => Mux~0.IN33
instrReg[14] => Mux~1.IN33
instrReg[14] => Mux~2.IN33
instrReg[14] => Mux~3.IN33
instrReg[14] => Mux~4.IN33
instrReg[14] => Mux~5.IN33
instrReg[14] => Mux~6.IN33
instrReg[14] => Mux~7.IN33
instrReg[14] => Mux~8.IN28
instrReg[14] => Mux~9.IN28
instrReg[14] => Mux~10.IN28
instrReg[14] => Mux~11.IN33
instrReg[14] => Mux~12.IN33
instrReg[14] => Mux~13.IN17
instrReg[15] => Mux~0.IN32
instrReg[15] => Mux~1.IN32
instrReg[15] => Mux~2.IN32
instrReg[15] => Mux~3.IN32
instrReg[15] => Mux~4.IN32
instrReg[15] => Mux~5.IN32
instrReg[15] => Mux~6.IN32
instrReg[15] => Mux~7.IN32
instrReg[15] => Mux~8.IN27
instrReg[15] => Mux~9.IN27
instrReg[15] => Mux~10.IN27
instrReg[15] => Mux~11.IN32
instrReg[15] => Mux~12.IN32
instrReg[15] => Mux~13.IN16
compout => next_state.bgti5.DATAB
compout => next_state.incpc.IN7
ready => next_state.execute.IN1
ready => regSel~0.OUTPUTSELECT
ready => regSel~1.OUTPUTSELECT
ready => regSel~2.OUTPUTSELECT
ready => Select~8.IN2
ready => next_state.incpc.IN2
ready => Select~2.IN2
ready => next_state.loadpc.IN1
ready => Select~2.IN3
ready => next_state.loadpc.IN2
ready => next_state.execute.IN2
ready => next_state.execute.IN3
ready => next_state.reset6.IN4
ready => next_state.incpc6.IN4
ready => next_state.loadpc4.IN4
ready => next_state.bgti10.IN4
ready => next_state.brai6.IN4
ready => next_state.loadi6.IN4
progCntrWr <= Select~2.DB_MAX_OUTPUT_PORT_TYPE
progCntrRd <= Select~7.DB_MAX_OUTPUT_PORT_TYPE
addrRegWr <= reduce_or~18.DB_MAX_OUTPUT_PORT_TYPE
addrRegRd <= <GND>
outRegWr <= reduce_or~14.DB_MAX_OUTPUT_PORT_TYPE
outRegRd <= reduce_or~15.DB_MAX_OUTPUT_PORT_TYPE
shiftSel[0] <= <GND>
shiftSel[1] <= <GND>
shiftSel[2] <= <GND>
aluSel[0] <= Select~1.DB_MAX_OUTPUT_PORT_TYPE
aluSel[1] <= Select~0.DB_MAX_OUTPUT_PORT_TYPE
aluSel[2] <= Select~0.DB_MAX_OUTPUT_PORT_TYPE
aluSel[3] <= aluSel~0.DB_MAX_OUTPUT_PORT_TYPE
compSel[0] <= <GND>
compSel[1] <= compSel~0.DB_MAX_OUTPUT_PORT_TYPE
compSel[2] <= <GND>
opRegRd <= compSel~0.DB_MAX_OUTPUT_PORT_TYPE
opRegWr <= current_state.bgti2.DB_MAX_OUTPUT_PORT_TYPE
instrWr <= next_state.execute.DB_MAX_OUTPUT_PORT_TYPE
regSel[0] <= Select~5.DB_MAX_OUTPUT_PORT_TYPE
regSel[1] <= Select~4.DB_MAX_OUTPUT_PORT_TYPE
regSel[2] <= Select~3.DB_MAX_OUTPUT_PORT_TYPE
regRd <= Select~6.DB_MAX_OUTPUT_PORT_TYPE
regWr <= Select~8.DB_MAX_OUTPUT_PORT_TYPE
rw <= current_state.store3.DB_MAX_OUTPUT_PORT_TYPE
vma <= reduce_or~19.DB_MAX_OUTPUT_PORT_TYPE


|top|comp:inst1
a[0] => nequal~0.IN0
a[0] => LessThan~0.IN16
a[0] => LessThan~1.IN16
a[0] => LessThan~2.IN16
a[0] => LessThan~3.IN16
a[1] => nequal~1.IN0
a[1] => LessThan~0.IN15
a[1] => LessThan~1.IN15
a[1] => LessThan~2.IN15
a[1] => LessThan~3.IN15
a[2] => nequal~2.IN0
a[2] => LessThan~0.IN14
a[2] => LessThan~1.IN14
a[2] => LessThan~2.IN14
a[2] => LessThan~3.IN14
a[3] => nequal~3.IN0
a[3] => LessThan~0.IN13
a[3] => LessThan~1.IN13
a[3] => LessThan~2.IN13
a[3] => LessThan~3.IN13
a[4] => nequal~4.IN0
a[4] => LessThan~0.IN12
a[4] => LessThan~1.IN12
a[4] => LessThan~2.IN12
a[4] => LessThan~3.IN12
a[5] => nequal~5.IN0
a[5] => LessThan~0.IN11
a[5] => LessThan~1.IN11
a[5] => LessThan~2.IN11
a[5] => LessThan~3.IN11
a[6] => nequal~6.IN0
a[6] => LessThan~0.IN10
a[6] => LessThan~1.IN10
a[6] => LessThan~2.IN10
a[6] => LessThan~3.IN10
a[7] => nequal~7.IN0
a[7] => LessThan~0.IN9
a[7] => LessThan~1.IN9
a[7] => LessThan~2.IN9
a[7] => LessThan~3.IN9
a[8] => nequal~8.IN0
a[8] => LessThan~0.IN8
a[8] => LessThan~1.IN8
a[8] => LessThan~2.IN8
a[8] => LessThan~3.IN8
a[9] => nequal~9.IN0
a[9] => LessThan~0.IN7
a[9] => LessThan~1.IN7
a[9] => LessThan~2.IN7
a[9] => LessThan~3.IN7
a[10] => nequal~10.IN0
a[10] => LessThan~0.IN6
a[10] => LessThan~1.IN6
a[10] => LessThan~2.IN6
a[10] => LessThan~3.IN6
a[11] => nequal~11.IN0
a[11] => LessThan~0.IN5
a[11] => LessThan~1.IN5
a[11] => LessThan~2.IN5
a[11] => LessThan~3.IN5
a[12] => nequal~12.IN0
a[12] => LessThan~0.IN4
a[12] => LessThan~1.IN4
a[12] => LessThan~2.IN4
a[12] => LessThan~3.IN4
a[13] => nequal~13.IN0
a[13] => LessThan~0.IN3
a[13] => LessThan~1.IN3
a[13] => LessThan~2.IN3
a[13] => LessThan~3.IN3
a[14] => nequal~14.IN0
a[14] => LessThan~0.IN2
a[14] => LessThan~1.IN2
a[14] => LessThan~2.IN2
a[14] => LessThan~3.IN2
a[15] => nequal~15.IN0
a[15] => LessThan~0.IN1
a[15] => LessThan~1.IN1
a[15] => LessThan~2.IN1
a[15] => LessThan~3.IN1
b[0] => nequal~0.IN1
b[0] => LessThan~0.IN32
b[0] => LessThan~1.IN32
b[0] => LessThan~2.IN32
b[0] => LessThan~3.IN32
b[1] => nequal~1.IN1
b[1] => LessThan~0.IN31
b[1] => LessThan~1.IN31
b[1] => LessThan~2.IN31
b[1] => LessThan~3.IN31
b[2] => nequal~2.IN1
b[2] => LessThan~0.IN30
b[2] => LessThan~1.IN30
b[2] => LessThan~2.IN30
b[2] => LessThan~3.IN30
b[3] => nequal~3.IN1
b[3] => LessThan~0.IN29
b[3] => LessThan~1.IN29
b[3] => LessThan~2.IN29