control1.tan.qmsg

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

{ "Info" "ITDB_TH_RESULT" "current_state.move2 instrReg\[13\] clock -4.669 ns register " "Info: th for register \"current_state.move2\" (data pin = \"instrReg\[13\]\", clock pin = \"clock\") is -4.669 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.910 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 47 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { clock } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns current_state.move2 2 REG LC_X27_Y8_N7 3 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X27_Y8_N7; Fanout = 3; REG Node = 'current_state.move2'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.441 ns" { clock current_state.move2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.move2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.move2 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.594 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns instrReg\[13\] 1 PIN PIN_106 13 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_106; Fanout = 13; PIN Node = 'instrReg\[13\]'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { instrReg[13] } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.641 ns) + CELL(0.478 ns) 7.594 ns current_state.move2 2 REG LC_X27_Y8_N7 3 " "Info: 2: + IC(5.641 ns) + CELL(0.478 ns) = 7.594 ns; Loc. = LC_X27_Y8_N7; Fanout = 3; REG Node = 'current_state.move2'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "6.119 ns" { instrReg[13] current_state.move2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns 25.72 % " "Info: Total cell delay = 1.953 ns ( 25.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.641 ns 74.28 % " "Info: Total interconnect delay = 5.641 ns ( 74.28 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "7.594 ns" { instrReg[13] current_state.move2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.594 ns" { instrReg[13] instrReg[13]~out0 current_state.move2 } { 0.000ns 0.000ns 5.641ns } { 0.000ns 1.475ns 0.478ns } } }  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.move2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.move2 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "7.594 ns" { instrReg[13] current_state.move2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.594 ns" { instrReg[13] instrReg[13]~out0 current_state.move2 } { 0.000ns 0.000ns 5.641ns } { 0.000ns 1.475ns 0.478ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 25 16:55:10 2006 " "Info: Processing ended: Tue Apr 25 16:55:10 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}