control1.tan.qmsg

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register current_state.inc4 register current_state.incpc 250.19 MHz 3.997 ns Internal " "Info: Clock \"clock\" has Internal fmax of 250.19 MHz between source register \"current_state.inc4\" and destination register \"current_state.incpc\" (period= 3.997 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.736 ns + Longest register register " "Info: + Longest register to register delay is 3.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.inc4 1 REG LC_X26_Y8_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y8_N2; Fanout = 2; REG Node = 'current_state.inc4'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { current_state.inc4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.590 ns) 1.118 ns reduce_or~307 2 COMB LC_X26_Y8_N3 2 " "Info: 2: + IC(0.528 ns) + CELL(0.590 ns) = 1.118 ns; Loc. = LC_X26_Y8_N3; Fanout = 2; COMB Node = 'reduce_or~307'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.118 ns" { current_state.inc4 reduce_or~307 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.105 ns) + CELL(0.590 ns) 2.813 ns Select~893 3 COMB LC_X26_Y8_N7 3 " "Info: 3: + IC(1.105 ns) + CELL(0.590 ns) = 2.813 ns; Loc. = LC_X26_Y8_N7; Fanout = 3; COMB Node = 'Select~893'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.695 ns" { reduce_or~307 Select~893 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.478 ns) 3.736 ns current_state.incpc 4 REG LC_X26_Y8_N1 2 " "Info: 4: + IC(0.445 ns) + CELL(0.478 ns) = 3.736 ns; Loc. = LC_X26_Y8_N1; Fanout = 2; REG Node = 'current_state.incpc'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "0.923 ns" { Select~893 current_state.incpc } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.658 ns 44.38 % " "Info: Total cell delay = 1.658 ns ( 44.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.078 ns 55.62 % " "Info: Total interconnect delay = 2.078 ns ( 55.62 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "3.736 ns" { current_state.inc4 reduce_or~307 Select~893 current_state.incpc } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.736 ns" { current_state.inc4 reduce_or~307 Select~893 current_state.incpc } { 0.000ns 0.528ns 1.105ns 0.445ns } { 0.000ns 0.590ns 0.590ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.910 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 47 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { clock } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns current_state.incpc 2 REG LC_X26_Y8_N1 2 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X26_Y8_N1; Fanout = 2; REG Node = 'current_state.incpc'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.441 ns" { clock current_state.incpc } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.incpc } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.incpc } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.910 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 47 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { clock } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns current_state.inc4 2 REG LC_X26_Y8_N2 2 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X26_Y8_N2; Fanout = 2; REG Node = 'current_state.inc4'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.441 ns" { clock current_state.inc4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.inc4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.inc4 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.incpc } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.incpc } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.inc4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.inc4 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "3.736 ns" { current_state.inc4 reduce_or~307 Select~893 current_state.incpc } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.736 ns" { current_state.inc4 reduce_or~307 Select~893 current_state.incpc } { 0.000ns 0.528ns 1.105ns 0.445ns } { 0.000ns 0.590ns 0.590ns 0.478ns } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.incpc } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.incpc } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.inc4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.inc4 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.incpc instrReg\[12\] clock 6.962 ns register " "Info: tsu for register \"current_state.incpc\" (data pin = \"instrReg\[12\]\", clock pin = \"clock\") is 6.962 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.835 ns + Longest pin register " "Info: + Longest pin to register delay is 9.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns instrReg\[12\] 1 PIN PIN_138 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_138; Fanout = 9; PIN Node = 'instrReg\[12\]'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { instrReg[12] } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.760 ns) + CELL(0.590 ns) 7.819 ns Mux~93 2 COMB LC_X28_Y8_N1 1 " "Info: 2: + IC(5.760 ns) + CELL(0.590 ns) = 7.819 ns; Loc. = LC_X28_Y8_N1; Fanout = 1; COMB Node = 'Mux~93'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "6.350 ns" { instrReg[12] Mux~93 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.083 ns) + CELL(0.442 ns) 9.344 ns next_state.incpc~34 3 COMB LC_X26_Y8_N0 1 " "Info: 3: + IC(1.083 ns) + CELL(0.442 ns) = 9.344 ns; Loc. = LC_X26_Y8_N0; Fanout = 1; COMB Node = 'next_state.incpc~34'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.525 ns" { Mux~93 next_state.incpc~34 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 9.835 ns current_state.incpc 4 REG LC_X26_Y8_N1 2 " "Info: 4: + IC(0.182 ns) + CELL(0.309 ns) = 9.835 ns; Loc. = LC_X26_Y8_N1; Fanout = 2; REG Node = 'current_state.incpc'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "0.491 ns" { next_state.incpc~34 current_state.incpc } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.810 ns 28.57 % " "Info: Total cell delay = 2.810 ns ( 28.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.025 ns 71.43 % " "Info: Total interconnect delay = 7.025 ns ( 71.43 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "9.835 ns" { instrReg[12] Mux~93 next_state.incpc~34 current_state.incpc } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.835 ns" { instrReg[12] instrReg[12]~out0 Mux~93 next_state.incpc~34 current_state.incpc } { 0.000ns 0.000ns 5.760ns 1.083ns 0.182ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.910 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 47 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { clock } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns current_state.incpc 2 REG LC_X26_Y8_N1 2 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X26_Y8_N1; Fanout = 2; REG Node = 'current_state.incpc'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.441 ns" { clock current_state.incpc } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.incpc } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.incpc } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "9.835 ns" { instrReg[12] Mux~93 next_state.incpc~34 current_state.incpc } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.835 ns" { instrReg[12] instrReg[12]~out0 Mux~93 next_state.incpc~34 current_state.incpc } { 0.000ns 0.000ns 5.760ns 1.083ns 0.182ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.309ns } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.incpc } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.incpc } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock aluSel\[0\] current_state.loadi2 13.358 ns register " "Info: tco from clock \"clock\" to destination pin \"aluSel\[0\]\" through register \"current_state.loadi2\" is 13.358 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.910 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 47 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 47; CLK Node = 'clock'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { clock } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns current_state.loadi2 2 REG LC_X25_Y7_N6 2 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X25_Y7_N6; Fanout = 2; REG Node = 'current_state.loadi2'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.441 ns" { clock current_state.loadi2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.loadi2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.loadi2 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.224 ns + Longest register pin " "Info: + Longest register to pin delay is 10.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.loadi2 1 REG LC_X25_Y7_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y7_N6; Fanout = 2; REG Node = 'current_state.loadi2'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { current_state.loadi2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.161 ns) + CELL(0.590 ns) 1.751 ns Select~886 2 COMB LC_X27_Y7_N4 2 " "Info: 2: + IC(1.161 ns) + CELL(0.590 ns) = 1.751 ns; Loc. = LC_X27_Y7_N4; Fanout = 2; COMB Node = 'Select~886'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.751 ns" { current_state.loadi2 Select~886 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.133 ns) + CELL(0.292 ns) 3.176 ns Select~887 3 COMB LC_X27_Y7_N9 2 " "Info: 3: + IC(1.133 ns) + CELL(0.292 ns) = 3.176 ns; Loc. = LC_X27_Y7_N9; Fanout = 2; COMB Node = 'Select~887'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.425 ns" { Select~886 Select~887 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.261 ns) + CELL(0.114 ns) 4.551 ns Select~889 4 COMB LC_X28_Y8_N7 3 " "Info: 4: + IC(1.261 ns) + CELL(0.114 ns) = 4.551 ns; Loc. = LC_X28_Y8_N7; Fanout = 3; COMB Node = 'Select~889'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.375 ns" { Select~887 Select~889 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.292 ns) 6.395 ns Select~890 5 COMB LC_X25_Y6_N4 1 " "Info: 5: + IC(1.552 ns) + CELL(0.292 ns) = 6.395 ns; Loc. = LC_X25_Y6_N4; Fanout = 1; COMB Node = 'Select~890'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.844 ns" { Select~889 Select~890 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.721 ns) + CELL(2.108 ns) 10.224 ns aluSel\[0\] 6 PIN PIN_101 0 " "Info: 6: + IC(1.721 ns) + CELL(2.108 ns) = 10.224 ns; Loc. = PIN_101; Fanout = 0; PIN Node = 'aluSel\[0\]'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "3.829 ns" { Select~890 aluSel[0] } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.396 ns 33.22 % " "Info: Total cell delay = 3.396 ns ( 33.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.828 ns 66.78 % " "Info: Total interconnect delay = 6.828 ns ( 66.78 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "10.224 ns" { current_state.loadi2 Select~886 Select~887 Select~889 Select~890 aluSel[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.224 ns" { current_state.loadi2 Select~886 Select~887 Select~889 Select~890 aluSel[0] } { 0.000ns 1.161ns 1.133ns 1.261ns 1.552ns 1.721ns } { 0.000ns 0.590ns 0.292ns 0.114ns 0.292ns 2.108ns } } }  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.910 ns" { clock current_state.loadi2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock clock~out0 current_state.loadi2 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "10.224 ns" { current_state.loadi2 Select~886 Select~887 Select~889 Select~890 aluSel[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.224 ns" { current_state.loadi2 Select~886 Select~887 Select~889 Select~890 aluSel[0] } { 0.000ns 1.161ns 1.133ns 1.261ns 1.552ns 1.721ns } { 0.000ns 0.590ns 0.292ns 0.114ns 0.292ns 2.108ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "instrReg\[12\] regSel\[1\] 15.613 ns Longest " "Info: Longest tpd from source pin \"instrReg\[12\]\" to destination pin \"regSel\[1\]\" is 15.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns instrReg\[12\] 1 PIN PIN_138 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_138; Fanout = 9; PIN Node = 'instrReg\[12\]'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { instrReg[12] } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.761 ns) + CELL(0.590 ns) 7.820 ns Select~895 2 COMB LC_X28_Y8_N0 1 " "Info: 2: + IC(5.761 ns) + CELL(0.590 ns) = 7.820 ns; Loc. = LC_X28_Y8_N0; Fanout = 1; COMB Node = 'Select~895'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "6.351 ns" { instrReg[12] Select~895 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.114 ns) 8.361 ns Select~896 3 COMB LC_X28_Y8_N2 1 " "Info: 3: + IC(0.427 ns) + CELL(0.114 ns) = 8.361 ns; Loc. = LC_X28_Y8_N2; Fanout = 1; COMB Node = 'Select~896'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "0.541 ns" { Select~895 Select~896 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.577 ns) + CELL(0.292 ns) 10.230 ns Select~903 4 COMB LC_X26_Y7_N4 3 " "Info: 4: + IC(1.577 ns) + CELL(0.292 ns) = 10.230 ns; Loc. = LC_X26_Y7_N4; Fanout = 3; COMB Node = 'Select~903'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.869 ns" { Select~896 Select~903 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.584 ns) + CELL(0.292 ns) 12.106 ns Select~898 5 COMB LC_X30_Y4_N5 1 " "Info: 5: + IC(1.584 ns) + CELL(0.292 ns) = 12.106 ns; Loc. = LC_X30_Y4_N5; Fanout = 1; COMB Node = 'Select~898'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "1.876 ns" { Select~903 Select~898 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.399 ns) + CELL(2.108 ns) 15.613 ns regSel\[1\] 6 PIN PIN_114 0 " "Info: 6: + IC(1.399 ns) + CELL(2.108 ns) = 15.613 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'regSel\[1\]'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "3.507 ns" { Select~898 regSel[1] } "NODE_NAME" } "" } } { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.865 ns 31.16 % " "Info: Total cell delay = 4.865 ns ( 31.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.748 ns 68.84 % " "Info: Total interconnect delay = 10.748 ns ( 68.84 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "15.613 ns" { instrReg[12] Select~895 Select~896 Select~903 Select~898 regSel[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "15.613 ns" { instrReg[12] instrReg[12]~out0 Select~895 Select~896 Select~903 Select~898 regSel[1] } { 0.000ns 0.000ns 5.761ns 0.427ns 1.577ns 1.584ns 1.399ns } { 0.000ns 1.469ns 0.590ns 0.114ns 0.292ns 0.292ns 2.108ns } } }  } 0}