control1.fit.qmsg

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.369 ns register register " "Info: Estimated most critical path is register to register delay of 2.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.inc4 1 REG LAB_X26_Y8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y8; Fanout = 2; REG Node = 'current_state.inc4'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { current_state.inc4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.679 ns) + CELL(0.114 ns) 0.793 ns reduce_or~307 2 COMB LAB_X26_Y8 2 " "Info: 2: + IC(0.679 ns) + CELL(0.114 ns) = 0.793 ns; Loc. = LAB_X26_Y8; Fanout = 2; COMB Node = 'reduce_or~307'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "0.793 ns" { current_state.inc4 reduce_or~307 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.590 ns) 1.510 ns Select~893 3 COMB LAB_X26_Y8 3 " "Info: 3: + IC(0.127 ns) + CELL(0.590 ns) = 1.510 ns; Loc. = LAB_X26_Y8; Fanout = 3; COMB Node = 'Select~893'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "0.717 ns" { reduce_or~307 Select~893 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.309 ns) 2.369 ns current_state.incpc 4 REG LAB_X26_Y8 2 " "Info: 4: + IC(0.550 ns) + CELL(0.309 ns) = 2.369 ns; Loc. = LAB_X26_Y8; Fanout = 2; REG Node = 'current_state.incpc'" {  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "0.859 ns" { Select~893 current_state.incpc } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.013 ns 42.76 % " "Info: Total cell delay = 1.013 ns ( 42.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.356 ns 57.24 % " "Info: Total interconnect delay = 1.356 ns ( 57.24 % )" {  } {  } 0}  } { { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "2.369 ns" { current_state.inc4 reduce_or~307 Select~893 current_state.incpc } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 3 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 3%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "6 " "Warning: The following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "addrRegRd GND " "Info: Pin addrRegRd has GND driving its datain port" {  } { { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 13 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "addrRegRd" } } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { addrRegRd } "NODE_NAME" } "" } } { "E:/cpu_a/control1.fld" "" { Floorplan "E:/cpu_a/control1.fld" "" "" { addrRegRd } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "shiftSel\[0\] GND " "Info: Pin shiftSel\[0\] has GND driving its datain port" {  } { { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 16 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "shiftSel\[0\]" } } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { shiftSel[0] } "NODE_NAME" } "" } } { "E:/cpu_a/control1.fld" "" { Floorplan "E:/cpu_a/control1.fld" "" "" { shiftSel[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "shiftSel\[1\] GND " "Info: Pin shiftSel\[1\] has GND driving its datain port" {  } { { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 16 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "shiftSel\[1\]" } } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { shiftSel[1] } "NODE_NAME" } "" } } { "E:/cpu_a/control1.fld" "" { Floorplan "E:/cpu_a/control1.fld" "" "" { shiftSel[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "shiftSel\[2\] GND " "Info: Pin shiftSel\[2\] has GND driving its datain port" {  } { { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 16 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "shiftSel\[2\]" } } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { shiftSel[2] } "NODE_NAME" } "" } } { "E:/cpu_a/control1.fld" "" { Floorplan "E:/cpu_a/control1.fld" "" "" { shiftSel[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "compSel\[0\] GND " "Info: Pin compSel\[0\] has GND driving its datain port" {  } { { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 18 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "compSel\[0\]" } } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { compSel[0] } "NODE_NAME" } "" } } { "E:/cpu_a/control1.fld" "" { Floorplan "E:/cpu_a/control1.fld" "" "" { compSel[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "compSel\[2\] GND " "Info: Pin compSel\[2\] has GND driving its datain port" {  } { { "control1.vhd" "" { Text "E:/cpu_a/control1.vhd" 18 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "compSel\[2\]" } } } } { "E:/cpu_a/db/control1_cmp.qrpt" "" { Report "E:/cpu_a/db/control1_cmp.qrpt" Compiler "control1" "UNKNOWN" "V1" "E:/cpu_a/db/control1.quartus_db" { Floorplan "E:/cpu_a/" "" "" { compSel[2] } "NODE_NAME" } "" } } { "E:/cpu_a/control1.fld" "" { Floorplan "E:/cpu_a/control1.fld" "" "" { compSel[2] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 25 16:54:58 2006 " "Info: Processing ended: Tue Apr 25 16:54:58 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0}  } {  } 0}