top.map.qmsg

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 08 10:41:38 2006 " "Info: Processing started: Sun Oct 08 10:41:38 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off top -c top " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off top -c top" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_lib.VHD 1 0 " "Info: Found 1 design units, including 0 entities, in source file cpu_lib.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_lib " "Info: Found design unit 1: cpu_lib" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/cpu_lib.VHD" "cpu_lib" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/cpu_lib.VHD" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "top.bdf 1 1 " "Info: Using design file top.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/top.bdf" "top" "" { Schematic "D:/16BITCPU/CH6_Expt/DEMO_62/top.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "control1.vhd 2 1 " "Info: Using design file control1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 control1-rtl " "Info: Found design unit 1: control1-rtl" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/control1.vhd" "control1-rtl" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/control1.vhd" 28 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 control1 " "Info: Found entity 1: control1" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/control1.vhd" "control1" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/control1.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "comp.vhd 2 1 " "Info: Using design file comp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 comp-rtl " "Info: Found design unit 1: comp-rtl" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/comp.vhd" "comp-rtl" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/comp.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 comp " "Info: Found entity 1: comp" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/comp.vhd" "comp" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/comp.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "reg_l.vhd 2 1 " "Info: Using design file reg_l.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg_l-Behavioral " "Info: Found design unit 1: reg_l-Behavioral" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/reg_l.vhd" "reg_l-Behavioral" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/reg_l.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg_l " "Info: Found entity 1: reg_l" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/reg_l.vhd" "reg_l" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/reg_l.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "STEP9.vqm 1 1 " "Info: Using design file STEP9.vqm, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 STEP9 " "Info: Found entity 1: STEP9" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/STEP9.vqm" "STEP9" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/STEP9.vqm" 27 14 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "trireg.vhd 2 1 " "Info: Using design file trireg.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 trireg-rtl " "Info: Found design unit 1: trireg-rtl" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/trireg.vhd" "trireg-rtl" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/trireg.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 trireg " "Info: Found entity 1: trireg" {  } { { "D:/16BITCPU/CH6_Expt/DEMO_62/trireg.vhd" "trireg" "" { Text "D:/16BITCPU/CH6_Expt/DEMO_62/trireg.vhd" 5 -1 0 } }  } 0}  } {  } 0}