step9.vqm

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.1 Build 181 06/29/2004 SJ Full Version"

// DATE "10/08/2006 10:32:41"

module 	STEP9 (
	RESET,
	CLK,
	STEP,
	NESW,
	DOUT,
	XX0,
	XX1,
	XX2,
	T1,
	T2,
	T3,
	T4,
	POE);
input 	RESET;
input 	CLK;
input 	STEP;
input 	NESW;
output 	DOUT;
output 	XX0;
output 	XX1;
output 	XX2;
output 	T1;
output 	T2;
output 	T3;
output 	T4;
output 	[7:0] POE;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0~COUT ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[0]~COUT0 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[0]~COUT1 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[0] ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1~COUT ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[1]~COUT0 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[1]~COUT1 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[1] ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2~COUT ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[2]~COUT0 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[2]~COUT1 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[2] ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3~COUT ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[3]~COUT0 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[3]~COUT1 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[3] ;
wire \SCHKT:inst1|CLKA~59 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4~COUT ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[4] ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5~COUT ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[5]~COUT0 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[5]~COUT1 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[5] ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella6~COUT ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[6]~COUT0 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[6]~COUT1 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[6] ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella7~COUT ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[7]~COUT0 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[7]~COUT1 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[7] ;
wire \SCHKT:inst1|CLKA~60 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella8~COUT ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[8]~COUT0 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[8]~COUT1 ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[8] ;
wire \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[9] ;
wire \SCHKT:inst1|CLKA~61 ;
wire \NESW~combout ;
wire \SCHKT:inst1|Mux~3600 ;
wire \SCHKT:inst1|LOK[0] ;
wire \SCHKT:inst1|CT2[1] ;
wire \SCHKT:inst1|LOK[1] ;
wire \SCHKT:inst1|Mux~3279 ;
wire \SCHKT:inst1|Mux~3287 ;
wire \SCHKT:inst1|Mux~3288 ;
wire \SCHKT:inst1|Mux~3294 ;
wire \RESET~combout ;
wire \SCHKT:inst1|Q[1] ;
wire \SCHKT:inst1|Mux~109 ;
wire \SCHKT:inst1|Mux~3601 ;
wire \SCHKT:inst1|Mux~3605 ;
wire \SCHKT:inst1|Mux~3606 ;
wire \SCHKT:inst1|Mux~160 ;
wire \SCHKT:inst1|Q[3] ;
wire \SCHKT:inst1|Mux~111 ;
wire \SCHKT:inst1|Mux~3591 ;
wire \SCHKT:inst1|Mux~114 ;
wire \SCHKT:inst1|add~9 ;
wire \SCHKT:inst1|CT2[2] ;
wire \SCHKT:inst1|Mux~3594 ;
wire \SCHKT:inst1|process0~2 ;
wire \SCHKT:inst1|Mux~3581 ;
wire \SCHKT:inst1|Mux~161 ;
wire \SCHKT:inst1|Mux~162 ;
wire \SCHKT:inst1|Q[0] ;
wire \SCHKT:inst1|Mux~3596 ;
wire \SCHKT:inst1|Mux~3597 ;
wire \SCHKT:inst1|LOK[2] ;
wire \SCHKT:inst1|Mux~3415 ;
wire \SCHKT:inst1|Mux~3603 ;
wire \SCHKT:inst1|Mux~3598 ;
wire \SCHKT:inst1|Mux~163 ;
wire \SCHKT:inst1|Mux~3604 ;
wire \SCHKT:inst1|Q[4] ;
wire \SCHKT:inst1|process0~0 ;
wire \SCHKT:inst1|Q[5] ;
wire \SCHKT:inst1|Mux~3592 ;
wire \SCHKT:inst1|Mux~3588 ;
wire \SCHKT:inst1|Mux~3589 ;
wire \SCHKT:inst1|Mux~3590 ;
wire \SCHKT:inst1|Q[2] ;
wire \SCHKT:inst1|A1~24 ;
wire \SCHKT:inst1|A1~22 ;
wire \SCHKT:inst1|ENA ;
wire \STEP~combout ;
wire \step:inst7|t2 ;
wire \step:inst7|t3 ;
wire \step:inst7|t4 ;
wire \step:inst7|t1 ;
wire inst11;
wire \CLK~combout ;
wire \step:inst7|clk ;
wire inst8;
wire inst9;
wire inst10;
wire \SCHKT:inst1|FA[2]~3 ;
wire \SCHKT:inst1|FA[1]~4 ;
wire \SCHKT:inst1|FA[0]~5 ;
wire [2:0] \SCHKT:inst1|CT2 ;
wire [5:0] \SCHKT:inst1|Q ;
wire [9:0] \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q ;
wire [2:0] \SCHKT:inst1|LOK ;

wire \SCHKT:inst1|__ALT_INV__LOK[0] ;

wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;

assign \SCHKT:inst1|__ALT_INV__LOK[0]  = ~ \SCHKT:inst1|LOK[0] ;

cyclone_lcell \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0 (
	.clk(\CLK~combout ),
	.datab(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[0] ),
	.aclr(gnd),
	.regout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[0] ),
	.cout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0~COUT ));
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0 .operation_mode = "arithmetic";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0 .synch_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0 .register_cascade_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0 .sum_lutc_input = "datac";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0 .lut_mask = "33CC";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0 .output_mode = "reg_only";

cyclone_lcell \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1 (
	.clk(\CLK~combout ),
	.dataa(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[1] ),
	.aclr(gnd),
	.cin(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella0~COUT ),
	.regout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[1] ),
	.cout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1~COUT ));
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1 .operation_mode = "arithmetic";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1 .synch_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1 .register_cascade_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1 .sum_lutc_input = "cin";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1 .lut_mask = "5A5F";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1 .output_mode = "reg_only";

cyclone_lcell \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2 (
	.clk(\CLK~combout ),
	.dataa(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[2] ),
	.aclr(gnd),
	.cin(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella1~COUT ),
	.regout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[2] ),
	.cout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2~COUT ));
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2 .operation_mode = "arithmetic";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2 .synch_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2 .register_cascade_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2 .sum_lutc_input = "cin";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2 .lut_mask = "A50A";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2 .output_mode = "reg_only";

cyclone_lcell \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3 (
	.clk(\CLK~combout ),
	.datab(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[3] ),
	.aclr(gnd),
	.cin(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella2~COUT ),
	.regout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[3] ),
	.cout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3~COUT ));
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3 .operation_mode = "arithmetic";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3 .synch_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3 .register_cascade_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3 .sum_lutc_input = "cin";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3 .lut_mask = "3C3F";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3 .output_mode = "reg_only";

cyclone_lcell \SCHKT:inst1|CLKA~59_I (
	.dataa(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[3] ),
	.datab(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[0] ),
	.datac(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[2] ),
	.datad(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[1] ),
	.combout(\SCHKT:inst1|CLKA~59 ));
defparam \SCHKT:inst1|CLKA~59_I .operation_mode = "normal";
defparam \SCHKT:inst1|CLKA~59_I .synch_mode = "off";
defparam \SCHKT:inst1|CLKA~59_I .register_cascade_mode = "off";
defparam \SCHKT:inst1|CLKA~59_I .sum_lutc_input = "datac";
defparam \SCHKT:inst1|CLKA~59_I .lut_mask = "7FFF";
defparam \SCHKT:inst1|CLKA~59_I .output_mode = "comb_only";

cyclone_lcell \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4 (
	.clk(\CLK~combout ),
	.datab(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[4] ),
	.aclr(gnd),
	.cin(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella3~COUT ),
	.regout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[4] ),
	.cout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4~COUT ));
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4 .operation_mode = "arithmetic";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4 .synch_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4 .register_cascade_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4 .sum_lutc_input = "cin";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4 .lut_mask = "C30C";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4 .output_mode = "reg_only";

cyclone_lcell \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5 (
	.clk(\CLK~combout ),
	.datab(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[5] ),
	.aclr(gnd),
	.cin(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella4~COUT ),
	.regout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[5] ),
	.cout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5~COUT ));
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5 .operation_mode = "arithmetic";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5 .synch_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5 .register_cascade_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5 .sum_lutc_input = "cin";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5 .lut_mask = "3C3F";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5 .output_mode = "reg_only";

cyclone_lcell \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella6 (
	.clk(\CLK~combout ),
	.dataa(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[6] ),
	.aclr(gnd),
	.cin(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella5~COUT ),
	.regout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|safe_q[6] ),
	.cout(\SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella6~COUT ));
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella6 .operation_mode = "arithmetic";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella6 .synch_mode = "off";
defparam \SCHKT:inst1|lpm_counter:CT8_rtl_0|cntr_pt6:auto_generated|counter_cella6 .register_cascade_mode = "off";