reg_l.vhd

来自「16位CUPIP核,完全运行的好的东西,可以直接拿来用的!」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned. ALL;
ENTITY reg_l IS
          PORT ( rst,clk, load: IN std_logic;
             d: IN std_logic_vector ( 15 downto 0 );
             q: BUFFER std_logic_vector ( 15 downto 0 ));
END reg_l;
ARCHITECTURE Behavioral OF reg_l IS
BEGIN
     pl: PROCESS (clk,rst )
      BEGIN
         IF rst = '1' THEN
             q <= ( OTHERS => '0' );
            ELSIF (clk'LAST_VALUE='0' and clk'EVENT and clk= '1' ) THEN
             IF load = '1' THEN
               q<=d;
             ELSE
               q<=q;
             END IF;
          END IF;
   END PROCESS;
END Behavioral;