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📄 top.fit.eqn

📁 16位CUPIP核,完全运行的好的东西,可以直接拿来用的!
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YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[8] = YB1_q_a[13]_PORT_A_data_out[12];

--YB1_q_a[12] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[12] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[12] = YB1_q_a[13]_PORT_A_data_out[11];

--YB1_q_a[11] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[11] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[11] = YB1_q_a[13]_PORT_A_data_out[10];

--YB1_q_a[7] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[7] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[7] = YB1_q_a[13]_PORT_A_data_out[9];

--YB1_q_a[2] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[2] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[2] = YB1_q_a[13]_PORT_A_data_out[8];

--YB1_q_a[5] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[5] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[5] = YB1_q_a[13]_PORT_A_data_out[7];

--YB1_q_a[1] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[1] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[1] = YB1_q_a[13]_PORT_A_data_out[6];

--YB1_q_a[6] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[6] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[6] = YB1_q_a[13]_PORT_A_data_out[5];

--YB1_q_a[14] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[14] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[14] = YB1_q_a[13]_PORT_A_data_out[4];

--YB1_q_a[3] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[3] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[3] = YB1_q_a[13]_PORT_A_data_out[3];

--YB1_q_a[9] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[9] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
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