top.fit.eqn

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

--L1_q[14] is reg:inst12|q[14] at LC_X20_Y14_N1
--operation mode is normal

L1_q[14]_sload_eqn = A1L031;
L1_q[14] = DFFEA(L1_q[14]_sload_eqn, GLOBAL(inst22), VCC, , , , );


--F1L96 is control1:inst3|progCntrRd~153 at LC_X21_Y14_N6
--operation mode is normal

L1_q[13]_qfbk = L1_q[13];
F1L96 = !L1_q[12] & L1_q[13]_qfbk & F1L86;

--L1_q[13] is reg:inst12|q[13] at LC_X21_Y14_N6
--operation mode is normal

L1_q[13]_sload_eqn = A1L621;
L1_q[13] = DFFEA(L1_q[13]_sload_eqn, GLOBAL(inst22), VCC, , , , );


--F1L03Q is control1:inst3|current_state~46 at LC_X20_Y11_N5
--operation mode is normal

F1L03Q_lut_out = F1L24Q # F1L74Q;
F1L03Q = DFFEA(F1L03Q_lut_out, GLOBAL(STEP), !RST, , , , );


--F1L42Q is control1:inst3|current_state~40 at LC_X20_Y9_N8
--operation mode is normal

F1L42Q_lut_out = F1L02Q # F1L06 # F1L63Q & !D1L66;
F1L42Q = DFFEA(F1L42Q_lut_out, GLOBAL(STEP), !RST, , , , );


--F1L73Q is control1:inst3|current_state~53 at LC_X20_Y9_N9
--operation mode is normal

F1L73Q_lut_out = D1L66 & F1L63Q;
F1L73Q = DFFEA(F1L73Q_lut_out, GLOBAL(STEP), !RST, , , , );


--F1L4 is control1:inst3|aluSel[1]~65 at LC_X26_Y10_N4
--operation mode is normal

F1L4 = !F1L73Q & F1L3 & !F1L42Q;


--F1L76 is control1:inst3|progCntrRd~1 at LC_X20_Y11_N0
--operation mode is normal

F1L13Q_qfbk = F1L13Q;
F1L76 = F1L03Q # F1L13Q_qfbk # F1L96 # !F1L4;

--F1L13Q is control1:inst3|current_state~47 at LC_X20_Y11_N0
--operation mode is normal

F1L13Q_sload_eqn = F1L03Q;
F1L13Q = DFFEA(F1L13Q_sload_eqn, GLOBAL(STEP), !RST, , , , );


--F1_addrRegWr is control1:inst3|addrRegWr at LC_X25_Y10_N6
--operation mode is normal

F1_addrRegWr = F1L13Q # F1L91Q # F1L61Q # !F1L56;


--F1L33Q is control1:inst3|current_state~49 at LC_X11_Y10_N6
--operation mode is normal

F1L33Q_lut_out = F1L23Q;
F1L33Q = DFFEA(F1L33Q_lut_out, GLOBAL(STEP), !RST, , , , );


--F1L19 is control1:inst3|vma~206 at LC_X11_Y10_N3
--operation mode is normal

F1L41Q_qfbk = F1L41Q;
F1L19 = !F1L33Q & !F1L41Q_qfbk & !F1L92Q;

--F1L41Q is control1:inst3|current_state~25 at LC_X11_Y10_N3
--operation mode is normal

F1L41Q_sload_eqn = F1L31Q;
F1L41Q = DFFEA(F1L41Q_sload_eqn, GLOBAL(STEP), !RST, , , , );


--YB1_q_a[13] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[13] at M4K_X17_Y11
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 128, Port A Width: 16, Port B Depth: 128, Port B Width: 16
--Port A Logical Depth: 128, Port A Logical Width: 16, Port B Logical Depth: 128, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[13] = YB1_q_a[13]_PORT_A_data_out[0];

--YB1_q_b[13] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_b[13] at M4K_X17_Y11
YB1_q_b[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_b[13]_PORT_A_data_in_reg = DFFE(YB1_q_b[13]_PORT_A_data_in, YB1_q_b[13]_clock_0, , , );
YB1_q_b[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_b[13]_PORT_B_data_in_reg = DFFE(YB1_q_b[13]_PORT_B_data_in, YB1_q_b[13]_clock_1, , , );
YB1_q_b[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_b[13]_PORT_A_address_reg = DFFE(YB1_q_b[13]_PORT_A_address, YB1_q_b[13]_clock_0, , , );
YB1_q_b[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_b[13]_PORT_B_address_reg = DFFE(YB1_q_b[13]_PORT_B_address, YB1_q_b[13]_clock_1, , , );
YB1_q_b[13]_PORT_A_write_enable = F1L02Q;
YB1_q_b[13]_PORT_A_write_enable_reg = DFFE(YB1_q_b[13]_PORT_A_write_enable, YB1_q_b[13]_clock_0, , , );
YB1_q_b[13]_PORT_B_write_enable = ZB1L83;
YB1_q_b[13]_PORT_B_write_enable_reg = DFFE(YB1_q_b[13]_PORT_B_write_enable, YB1_q_b[13]_clock_1, , , );
YB1_q_b[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_b[13]_clock_1 = GLOBAL(A1L51);
YB1_q_b[13]_PORT_B_data_out = MEMORY(YB1_q_b[13]_PORT_A_data_in_reg, YB1_q_b[13]_PORT_B_data_in_reg, YB1_q_b[13]_PORT_A_address_reg, YB1_q_b[13]_PORT_B_address_reg, YB1_q_b[13]_PORT_A_write_enable_reg, YB1_q_b[13]_PORT_B_write_enable_reg, , , YB1_q_b[13]_clock_0, YB1_q_b[13]_clock_1, , , , );
YB1_q_b[13] = YB1_q_b[13]_PORT_B_data_out[0];

--YB1_q_a[4] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[4] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[4] = YB1_q_a[13]_PORT_A_data_out[15];

--YB1_q_a[10] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[10] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[10] = YB1_q_a[13]_PORT_A_data_out[14];

--YB1_q_a[0] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[0] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = BUS(ZB1_ram_rom_data_reg[13], ZB1_ram_rom_data_reg[15], ZB1_ram_rom_data_reg[9], ZB1_ram_rom_data_reg[3], ZB1_ram_rom_data_reg[14], ZB1_ram_rom_data_reg[6], ZB1_ram_rom_data_reg[1], ZB1_ram_rom_data_reg[5], ZB1_ram_rom_data_reg[2], ZB1_ram_rom_data_reg[7], ZB1_ram_rom_data_reg[11], ZB1_ram_rom_data_reg[12], ZB1_ram_rom_data_reg[8], ZB1_ram_rom_data_reg[0], ZB1_ram_rom_data_reg[10], ZB1_ram_rom_data_reg[4]);
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = GLOBAL(E1_inst11);
YB1_q_a[13]_clock_1 = GLOBAL(A1L51);
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[0] = YB1_q_a[13]_PORT_A_data_out[13];

--YB1_q_a[8] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[8] at M4K_X17_Y11
YB1_q_a[13]_PORT_A_data_in = BUS(A1L621, A1L531, A1L011, A1L09, A1L031, A1L99, A1L48, A1L69, A1L78, A1L201, A1L811, A1L221, A1L601, A1L08, A1L411, A1L39);