reg_2.vhd

来自「16位CUPIP核,完全运行的好的东西,可以直接拿来用的!」· VHDL 代码 · 共 27 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith. ALL;
USE IEEE.std_logic_unsigned. ALL;
ENTITY ureg IS
     GENERIC ( size: INTEGER := 2 );
     PORT ( clk, reset,load: IN std_logic;
             rst, pst: IN std_logic;
              d: IN std_logic_vector ( size - 1 downto 0 );
              q: BUFFER std_logic_vector ( size - 1 downto 0 ));
END ureg;
ARCHITECTURE Behavioral OF ureg IS
BEGIN
p1: PROCESS ( reset,clk )
   BEGIN
        IF reset ='1' THEN
          q <= ( OTHERS =>'0' );
       ELSIF (clk'LAST_VALUE='0' and clk'EVENT and clk = '1' )  THEN
          IF load = '1' THEN
             q <= d;
          ELSE
             q<=q;
          END IF;
       END IF;
  END PROCESS;
END Behavioral;