top.map.eqn

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

K1_ramdata[0][14]_lut_out = A1L031;
K1_ramdata[0][14] = DFFEA(K1_ramdata[0][14]_lut_out, inst11, VCC, , K1L1, , );


--K1L902 is regarray:inst10|temp_data[14]~108
--operation mode is normal

K1L902 = F1L18 & (F1L58 # K1_ramdata[1][14]) # !F1L18 & !F1L58 & K1_ramdata[0][14];


--K1_ramdata[3][14] is regarray:inst10|ramdata[3][14]
--operation mode is normal

K1_ramdata[3][14]_lut_out = A1L031;
K1_ramdata[3][14] = DFFEA(K1_ramdata[3][14]_lut_out, inst11, VCC, , K1L4, , );


--K1L012 is regarray:inst10|temp_data[14]~109
--operation mode is normal

K1L012 = K1L902 & (K1_ramdata[3][14] # !F1L58) # !K1L902 & K1_ramdata[2][14] & F1L58;


--K1_ramdata[5][14] is regarray:inst10|ramdata[5][14]
--operation mode is normal

K1_ramdata[5][14]_lut_out = A1L031;
K1_ramdata[5][14] = DFFEA(K1_ramdata[5][14]_lut_out, inst11, VCC, , K1L6, , );


--K1_ramdata[6][14] is regarray:inst10|ramdata[6][14]
--operation mode is normal

K1_ramdata[6][14]_lut_out = A1L031;
K1_ramdata[6][14] = DFFEA(K1_ramdata[6][14]_lut_out, inst11, VCC, , K1L7, , );


--K1_ramdata[4][14] is regarray:inst10|ramdata[4][14]
--operation mode is normal

K1_ramdata[4][14]_lut_out = A1L031;
K1_ramdata[4][14] = DFFEA(K1_ramdata[4][14]_lut_out, inst11, VCC, , K1L5, , );


--K1L112 is regarray:inst10|temp_data[14]~110
--operation mode is normal

K1L112 = F1L58 & (F1L18 # K1_ramdata[6][14]) # !F1L58 & !F1L18 & K1_ramdata[4][14];


--K1_ramdata[7][14] is regarray:inst10|ramdata[7][14]
--operation mode is normal

K1_ramdata[7][14]_lut_out = A1L031;
K1_ramdata[7][14] = DFFEA(K1_ramdata[7][14]_lut_out, inst11, VCC, , K1L8, , );


--K1L212 is regarray:inst10|temp_data[14]~111
--operation mode is normal

K1L212 = K1L112 & (K1_ramdata[7][14] # !F1L18) # !K1L112 & K1_ramdata[5][14] & F1L18;


--A1L921 is gdfx_temp0[14]~1359
--operation mode is normal

A1L921 = F1L68 & !K1L212 # !F1L68 & (F1L98 & !K1L212 # !F1L98 & !K1L012);


--A1L031 is gdfx_temp0[14]~1360
--operation mode is normal

A1L031 = A1L721 & A1L821 & (!A1L921 # !F1L67);


--YB1_q_a[6] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 16, Port B Logical Depth: 128, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_a[6]_PORT_A_data_in = A1L99;
YB1_q_a[6]_PORT_A_data_in_reg = DFFE(YB1_q_a[6]_PORT_A_data_in, YB1_q_a[6]_clock_0, , , );
YB1_q_a[6]_PORT_B_data_in = ZB1_ram_rom_data_reg[6];
YB1_q_a[6]_PORT_B_data_in_reg = DFFE(YB1_q_a[6]_PORT_B_data_in, YB1_q_a[6]_clock_1, , , );
YB1_q_a[6]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[6]_PORT_A_address_reg = DFFE(YB1_q_a[6]_PORT_A_address, YB1_q_a[6]_clock_0, , , );
YB1_q_a[6]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[6]_PORT_B_address_reg = DFFE(YB1_q_a[6]_PORT_B_address, YB1_q_a[6]_clock_1, , , );
YB1_q_a[6]_PORT_A_write_enable = F1L02Q;
YB1_q_a[6]_PORT_A_write_enable_reg = DFFE(YB1_q_a[6]_PORT_A_write_enable, YB1_q_a[6]_clock_0, , , );
YB1_q_a[6]_PORT_B_write_enable = ZB1L83;
YB1_q_a[6]_PORT_B_write_enable_reg = DFFE(YB1_q_a[6]_PORT_B_write_enable, YB1_q_a[6]_clock_1, , , );
YB1_q_a[6]_clock_0 = E1_inst11;
YB1_q_a[6]_clock_1 = A1L51;
YB1_q_a[6]_PORT_A_data_out = MEMORY(YB1_q_a[6]_PORT_A_data_in_reg, YB1_q_a[6]_PORT_B_data_in_reg, YB1_q_a[6]_PORT_A_address_reg, YB1_q_a[6]_PORT_B_address_reg, YB1_q_a[6]_PORT_A_write_enable_reg, YB1_q_a[6]_PORT_B_write_enable_reg, , , YB1_q_a[6]_clock_0, YB1_q_a[6]_clock_1, , , , );
YB1_q_a[6] = YB1_q_a[6]_PORT_A_data_out[0];

--YB1_q_b[6] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_b[6]
YB1_q_b[6]_PORT_A_data_in = A1L99;
YB1_q_b[6]_PORT_A_data_in_reg = DFFE(YB1_q_b[6]_PORT_A_data_in, YB1_q_b[6]_clock_0, , , );
YB1_q_b[6]_PORT_B_data_in = ZB1_ram_rom_data_reg[6];
YB1_q_b[6]_PORT_B_data_in_reg = DFFE(YB1_q_b[6]_PORT_B_data_in, YB1_q_b[6]_clock_1, , , );
YB1_q_b[6]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_b[6]_PORT_A_address_reg = DFFE(YB1_q_b[6]_PORT_A_address, YB1_q_b[6]_clock_0, , , );
YB1_q_b[6]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_b[6]_PORT_B_address_reg = DFFE(YB1_q_b[6]_PORT_B_address, YB1_q_b[6]_clock_1, , , );
YB1_q_b[6]_PORT_A_write_enable = F1L02Q;
YB1_q_b[6]_PORT_A_write_enable_reg = DFFE(YB1_q_b[6]_PORT_A_write_enable, YB1_q_b[6]_clock_0, , , );
YB1_q_b[6]_PORT_B_write_enable = ZB1L83;
YB1_q_b[6]_PORT_B_write_enable_reg = DFFE(YB1_q_b[6]_PORT_B_write_enable, YB1_q_b[6]_clock_1, , , );
YB1_q_b[6]_clock_0 = E1_inst11;
YB1_q_b[6]_clock_1 = A1L51;
YB1_q_b[6]_PORT_B_data_out = MEMORY(YB1_q_b[6]_PORT_A_data_in_reg, YB1_q_b[6]_PORT_B_data_in_reg, YB1_q_b[6]_PORT_A_address_reg, YB1_q_b[6]_PORT_B_address_reg, YB1_q_b[6]_PORT_A_write_enable_reg, YB1_q_b[6]_PORT_B_write_enable_reg, , , YB1_q_b[6]_clock_0, YB1_q_b[6]_clock_1, , , , );
YB1_q_b[6] = YB1_q_b[6]_PORT_B_data_out[0];


--A1L79 is gdfx_temp0[6]~1361
--operation mode is normal

A1L79 = YB1_q_a[6] & (in[6] # !M1_q[15]) # !F1L59;


--H1_val[6] is trireg:inst7|val[6]
--operation mode is normal

H1_val[6]_lut_out = C1L63;
H1_val[6] = DFFEA(H1_val[6]_lut_out, inst20, VCC, , , , );


--A1L89 is gdfx_temp0[6]~1362
--operation mode is normal

A1L89 = M2_q[6] & (H1_val[6] # !F1_outRegRd) # !M2_q[6] & !F1L76 & (H1_val[6] # !F1_outRegRd);


--K1_ramdata[5][6] is regarray:inst10|ramdata[5][6]
--operation mode is normal

K1_ramdata[5][6]_lut_out = A1L99;
K1_ramdata[5][6] = DFFEA(K1_ramdata[5][6]_lut_out, inst11, VCC, , K1L6, , );


--K1_ramdata[6][6] is regarray:inst10|ramdata[6][6]
--operation mode is normal

K1_ramdata[6][6]_lut_out = A1L99;
K1_ramdata[6][6] = DFFEA(K1_ramdata[6][6]_lut_out, inst11, VCC, , K1L7, , );


--K1_ramdata[4][6] is regarray:inst10|ramdata[4][6]
--operation mode is normal

K1_ramdata[4][6]_lut_out = A1L99;
K1_ramdata[4][6] = DFFEA(K1_ramdata[4][6]_lut_out, inst11, VCC, , K1L5, , );


--K1L771 is regarray:inst10|temp_data[6]~54
--operation mode is normal

K1L771 = F1L58 & (F1L18 # K1_ramdata[6][6]) # !F1L58 & !F1L18 & K1_ramdata[4][6];


--K1_ramdata[7][6] is regarray:inst10|ramdata[7][6]
--operation mode is normal

K1_ramdata[7][6]_lut_out = A1L99;
K1_ramdata[7][6] = DFFEA(K1_ramdata[7][6]_lut_out, inst11, VCC, , K1L8, , );


--K1L871 is regarray:inst10|temp_data[6]~55
--operation mode is normal

K1L871 = K1L771 & (K1_ramdata[7][6] # !F1L18) # !K1L771 & K1_ramdata[5][6] & F1L18;


--K1_ramdata[2][6] is regarray:inst10|ramdata[2][6]
--operation mode is normal

K1_ramdata[2][6]_lut_out = A1L99;
K1_ramdata[2][6] = DFFEA(K1_ramdata[2][6]_lut_out, inst11, VCC, , K1L3, , );


--K1_ramdata[1][6] is regarray:inst10|ramdata[1][6]
--operation mode is normal

K1_ramdata[1][6]_lut_out = A1L99;
K1_ramdata[1][6] = DFFEA(K1_ramdata[1][6]_lut_out, inst11, VCC, , K1L2, , );


--K1_ramdata[0][6] is regarray:inst10|ramdata[0][6]
--operation mode is normal

K1_ramdata[0][6]_lut_out = A1L99;
K1_ramdata[0][6] = DFFEA(K1_ramdata[0][6]_lut_out, inst11, VCC, , K1L1, , );


--K1L571 is regarray:inst10|temp_data[6]~52
--operation mode is normal

K1L571 = F1L18 & (F1L58 # K1_ramdata[1][6]) # !F1L18 & !F1L58 & K1_ramdata[0][6];


--K1_ramdata[3][6] is regarray:inst10|ramdata[3][6]
--operation mode is normal

K1_ramdata[3][6]_lut_out = A1L99;
K1_ramdata[3][6] = DFFEA(K1_ramdata[3][6]_lut_out, inst11, VCC, , K1L4, , );


--K1L671 is regarray:inst10|temp_data[6]~53
--operation mode is normal

K1L671 = K1L571 & (K1_ramdata[3][6] # !F1L58) # !K1L571 & K1_ramdata[2][6] & F1L58;


--K1L971 is regarray:inst10|temp_data[6]~3041
--operation mode is normal

K1L971 = F1L68 & K1L871 # !F1L68 & (F1L98 & K1L871 # !F1L98 & K1L671);


--A1L99 is gdfx_temp0[6]~1363
--operation mode is normal

A1L99 = A1L79 & A1L89 & (K1L971 # !F1L67);


--D1L4 is comp:inst1|compout~265
--operation mode is normal

D1L4 = M3_q[6] & A1L99 & (M3_q[14] $ !A1L031) # !M3_q[6] & !A1L99 & (M3_q[14] $ !A1L031);


--YB1_q_a[1] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 16, Port B Logical Depth: 128, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_a[1]_PORT_A_data_in = A1L48;
YB1_q_a[1]_PORT_A_data_in_reg = DFFE(YB1_q_a[1]_PORT_A_data_in, YB1_q_a[1]_clock_0, , , );
YB1_q_a[1]_PORT_B_data_in = ZB1_ram_rom_data_reg[1];
YB1_q_a[1]_PORT_B_data_in_reg = DFFE(YB1_q_a[1]_PORT_B_data_in, YB1_q_a[1]_clock_1, , , );
YB1_q_a[1]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[1]_PORT_A_address_reg = DFFE(YB1_q_a[1]_PORT_A_address, YB1_q_a[1]_clock_0, , , );
YB1_q_a[1]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[1]_PORT_B_address_reg = DFFE(YB1_q_a[1]_PORT_B_address, YB1_q_a[1]_clock_1, , , );
YB1_q_a[1]_PORT_A_write_enable = F1L02Q;
YB1_q_a[1]_PORT_A_write_enable_reg = DFFE(YB1_q_a[1]_PORT_A_write_enable, YB1_q_a[1]_clock_0, , , );
YB1_q_a[1]_PORT_B_write_enable = ZB1L83;
YB1_q_a[1]_PORT_B_write_enable_reg = DFFE(YB1_q_a[1]_PORT_B_write_enable, YB1_q_a[1]_clock_1, , , );
YB1_q_a[1]_clock_0 = E1_inst11;
YB1_q_a[1]_clock_1 = A1L51;
YB1_q_a[1]_PORT_A_data_out = MEMORY(YB1_q_a[1]_PORT_A_data_in_reg, YB1_q_a[1]_PORT_B_data_in_reg, YB1_q_a[1]_PORT_A_address_reg, YB1_q_a[1]_PORT_B_address_reg, YB1_q_a[1]_PORT_A_write_enable_reg, YB1_q_a[1]_PORT_B_write_enable_reg, , , YB1_q_a[1]_clock_0, YB1_q_a[1]_clock_1, , , , );
YB1_q_a[1] = YB1_q_a[1]_PORT_A_data_out[0];

--YB1_q_b[1] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_b[1]
YB1_q_b[1]_PORT_A_data_in = A1L48;
YB1_q_b[1]_PORT_A_data_in_reg = DFFE(YB1_q_b[1]_PORT_A_data_in, YB1_q_b[1]_clock_0, , , );
YB1_q_b[1]_PORT_B_data_in = ZB1_ram_rom_data_reg[1];
YB1_q_b[1]_PORT_B_data_in_reg = DFFE(YB1_q_b[1]_PORT_B_data_in, YB1_q_b[1]_clock_1, , , );
YB1_q_b[1]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_b[1]_PORT_A_address_reg = DFFE(YB1_q_b[1]_PORT_A_address, YB1_q_b[1]_clock_0, , , );
YB1_q_b[1]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_b[1]_PORT_B_address_reg = DFFE(YB1_q_b[1]_PORT_B_address, YB1_q_b[1]_clock_1, , , );
YB1_q_b[1]_PORT_A_write_enable = F1L02Q;
YB1_q_b[1]_PORT_A_write_enable_reg = DFFE(YB1_q_b[1]_PORT_A_write_enable, YB1_q_b[1]_clock_0, , , );
YB1_q_b[1]_PORT_B_write_enable = ZB1L83;
YB1_q_b[1]_PORT_B_write_enable_reg = DFFE(YB1_q_b[1]_PORT_B_write_enable, YB1_q_b[1]_clock_1, , , );
YB1_q_b[1]_clock_0 = E1_inst11;
YB1_q_b[1]_clock_1 = A1L51;
YB1_q_b[1]_PORT_B_data_out = MEMORY(YB1_q_b[1]_PORT_A_data_in_reg, YB1_q_b[1]_PORT_B_data_in_reg, YB1_q_b[1]_PORT_A_address_reg, YB1_q_b[1]_PORT_B_address_reg, YB1_q_b[1]_PORT_A_write_enable_reg, YB1_q_b[1]_PORT_B_write_enable_reg, , , YB1_q_b[1]_clock_0, YB1_q_b[1]_clock_1, , , , );
YB1_q_b[1] = YB1_q_b[1]_PORT_B_data_out[0];


--A1L28 is gdfx_temp0[1]~1364
--operation mode is normal

A1L28 = YB1_q_a[1] & (in[1] # !M1_q[15]) # !F1L59;


--H1_val[1] is trireg:inst7|val[1]
--operation mode is normal

H1_val[1]_lut_out = C1L64;
H1_val[1] = DFFEA(H1_val[1]_lut_out, inst20, VCC, , , , );


--A1L38 is gdfx_temp0[1]~1365
--operation mode is normal

A1L38 = M2_q[1] & (H1_val[1] # !F1_outRegRd) # !M2_q[1] & !F1L76 & (H1_val[1] # !F1_outRegRd);


--K1_ramdata[5][1] is regarray:inst10|ramdata[5][1]
--operation mode is normal

K1_ramdata[5][1]_lut_out = A1L48;
K1_ramdata[5][1] = DFFEA(K1_ramdata[5][1]_lut_out, inst11, VCC, , K1L6, , );


--K1_ramdata[6][1] is regarray:inst10|ramdata[6][1]
--operation mode is normal

K1_ramdata[6][1]_lut_out = A1L48;
K1_ramdata[6][1] = DFFEA(K1_ramdata[6][1]_lut_out, inst11, VCC, , K1L7, , );


--K1_ramdata[4][1] is regarray:inst10|ramdata[4][1]
--operation mode is normal

K1_ramdata[4][1]_lut_out = A1L48;
K1_ramdata[4][1] = DFFEA(K1_ramdata[4][1]_lut_out, inst11, VCC, , K1L5, , );


--K1L251 is regarray:inst10|temp_data[1]~74
--operation mode is normal

K1L251 = F1L58 & (F1L18 # K1_ramdata[6][1]) # !F1L58 & !F1L18 & K1_ramdata[4][1];


--K1_ramdata[7][1] is regarray:inst10|ramdata[7][1]
--operation mode is normal

K1_ramdata[7][1]_lut_out = A1L48;
K1_ramdata[7][1] = DFFEA(K1_ramdata[7][1]_lut_out, inst11, VCC, , K1L8, , );


--K1L351 is regarray:inst10|temp_data[1]~75
--operation mode is normal

K1L351 = K1L251 & (K1_ramdata[7][1] # !F1L18) # !K1L251 & K1_ramdata[5][1] & F1L18;


--K1_ramdata[2][1] is regarray:inst10|ramdata[2][1]
--operation mode is normal

K1_ramdata[2][1]_lut_out = A1L48;
K1_ramdata[2][1] = DFFEA(K1_ramdata[2][1]_lut_out, inst11, VCC, , K1L3, , );


--K1_ramdata[1][1] is regarray:inst10|ramdata[1][1]
--operation mode is normal

K1_ramdata[1][1]_lut_out = A1L48;
K1_ramdata[1][1] = DFFEA(K1_ramdata[1][1]_lut_out, inst11, VCC, , K1L2, , );


--K1_ramdata[0][1] is regarray:inst10|ramdata[0][1]
--operation mode is normal

K1_ramdata[0][1]_lut_out = A1L48;
K1_ramdata[0][1] = DFFEA(K1_ramdata[0][1]_lut_out, inst11, VCC, , K1L1, , );


--K1L051 is regarray:inst10|temp_data[1]~72
--operation mode is normal

K1L051 = F1L18 & (F1L58 # K1_ramdata[1][1]) # !F1L18 & !F1L58 & K1_ramdata[0][1];


--K1_ramdata[3][1] is regarray:inst10|ramdata[3][1]
--operation mode is normal

K1_ramdata[3][1]_lut_out = A1L48;
K1_ramdata[3][1] = DFFEA(K1_ramdata[3][1]_lut_out, inst11, VCC, , K1L4, , );


--K1L151 is regarray:inst10|temp_data[1]~73
--operation mode is normal

K1L151 = K1L051 & (K1_ramdata[3][1] # !F1L58) # !K1L051 & K1_ramdata[2][1] & F1L58;


--K1L451 is regarray:inst10|temp_data[1]~3042
--operation mode is normal

K1L451 = F1L68 & K1L351 # !F1L68 & (F1L98 & K1L351 # !F1L98 & K1L151);


--A1L48 is gdfx_temp0[1]~1366
--operation mode is normal

A1L48 = A1L28 & A1L38 & (K1L451 # !F1L67);


--YB1_q_a[5] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 16, Port B Logical Depth: 128, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_a[5]_PORT_A_data_in = A1L69;
YB1_q_a[5]_PORT_A_data_in_reg = DFFE(YB1_q_a[5]_PORT_A_data_in, YB1_q_a[5]_clock_0, , , );
YB1_q_a[5]_PORT_B_data_in = ZB1_ram_rom_data_reg[5];
YB1_q_a[5]_PORT_B_data_in_reg