top.map.eqn

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

F1L44Q_lut_out = F1L34Q;
F1L44Q = DFFEA(F1L44Q_lut_out, STEP, !RST, , , , );


--F1L94Q is control1:inst3|current_state~65
--operation mode is normal

F1L94Q_lut_out = F1L84Q;
F1L94Q = DFFEA(F1L94Q_lut_out, STEP, !RST, , , , );


--F1L36 is control1:inst3|outRegRd~196
--operation mode is normal

F1L36 = F1L62Q # F1L93Q # F1L44Q # F1L94Q;


--F1L21Q is control1:inst3|current_state~23
--operation mode is normal

F1L21Q_lut_out = F1L11Q;
F1L21Q = DFFEA(F1L21Q_lut_out, STEP, !RST, , , , );


--F1L72Q is control1:inst3|current_state~43
--operation mode is normal

F1L72Q_lut_out = F1L62Q;
F1L72Q = DFFEA(F1L72Q_lut_out, STEP, !RST, , , , );


--F1L46 is control1:inst3|outRegRd~197
--operation mode is normal

F1L46 = !F1L21Q & !F1L72Q;


--F1L05Q is control1:inst3|current_state~66
--operation mode is normal

F1L05Q_lut_out = F1L94Q;
F1L05Q = DFFEA(F1L05Q_lut_out, STEP, !RST, , , , );


--F1L04Q is control1:inst3|current_state~56
--operation mode is normal

F1L04Q_lut_out = F1L93Q;
F1L04Q = DFFEA(F1L04Q_lut_out, STEP, !RST, , , , );


--F1L54Q is control1:inst3|current_state~61
--operation mode is normal

F1L54Q_lut_out = F1L44Q;
F1L54Q = DFFEA(F1L54Q_lut_out, STEP, !RST, , , , );


--F1L56 is control1:inst3|outRegRd~198
--operation mode is normal

F1L56 = F1L46 & !F1L05Q & !F1L04Q & !F1L54Q;


--F1_outRegRd is control1:inst3|outRegRd
--operation mode is normal

F1_outRegRd = F1L45Q # F1L26 # F1L36 # !F1L56;


--F1L01Q is control1:inst3|current_state~21
--operation mode is normal

F1L01Q_lut_out = !F1L9Q;
F1L01Q = DFFEA(F1L01Q_lut_out, STEP, !RST, , , , );


--F1L52Q is control1:inst3|current_state~41
--operation mode is normal

F1L52Q_lut_out = F1L42Q;
F1L52Q = DFFEA(F1L52Q_lut_out, STEP, !RST, , , , );


--F1L83Q is control1:inst3|current_state~54
--operation mode is normal

F1L83Q_lut_out = F1L73Q;
F1L83Q = DFFEA(F1L83Q_lut_out, STEP, !RST, , , , );


--F1L34Q is control1:inst3|current_state~59
--operation mode is normal

F1L34Q_lut_out = L1_q[11] & L1_q[13] & F1L86 & !L1_q[12];
F1L34Q = DFFEA(F1L34Q_lut_out, STEP, !RST, , , , );


--F1L84Q is control1:inst3|current_state~64
--operation mode is normal

F1L84Q_lut_out = L1_q[13] & F1L86 & !L1_q[11] & !L1_q[12];
F1L84Q = DFFEA(F1L84Q_lut_out, STEP, !RST, , , , );


--F1L3 is control1:inst3|aluSel[1]~64
--operation mode is normal

F1L3 = !F1L52Q & !F1L83Q & !F1L34Q & !F1L84Q;


--F1_outRegWr is control1:inst3|outRegWr
--operation mode is normal

F1_outRegWr = F1L35Q # F1L12Q # F1L01Q # !F1L3;


--F1L24Q is control1:inst3|current_state~58
--operation mode is normal

F1L24Q_lut_out = F1L14Q;
F1L24Q = DFFEA(F1L24Q_lut_out, STEP, !RST, , , , );


--F1L74Q is control1:inst3|current_state~63
--operation mode is normal

F1L74Q_lut_out = F1L64Q;
F1L74Q = DFFEA(F1L74Q_lut_out, STEP, !RST, , , , );


--F1L07 is control1:inst3|progCntrWr~1
--operation mode is normal

F1L07 = F1L24Q # F1L74Q # !F1L56;


--F1L86 is control1:inst3|progCntrRd~152
--operation mode is normal

F1L86 = F1L51Q & !L1_q[14] & !L1_q[15];


--F1L96 is control1:inst3|progCntrRd~153
--operation mode is normal

F1L96 = L1_q[13] & F1L86 & !L1_q[12];


--F1L03Q is control1:inst3|current_state~46
--operation mode is normal

F1L03Q_lut_out = F1L24Q # F1L74Q;
F1L03Q = DFFEA(F1L03Q_lut_out, STEP, !RST, , , , );


--F1L13Q is control1:inst3|current_state~47
--operation mode is normal

F1L13Q_lut_out = F1L03Q;
F1L13Q = DFFEA(F1L13Q_lut_out, STEP, !RST, , , , );


--F1L42Q is control1:inst3|current_state~40
--operation mode is normal

F1L42Q_lut_out = F1L02Q # F1L06 # F1L63Q & !D1L24;
F1L42Q = DFFEA(F1L42Q_lut_out, STEP, !RST, , , , );


--F1L73Q is control1:inst3|current_state~53
--operation mode is normal

F1L73Q_lut_out = D1L24 & F1L63Q;
F1L73Q = DFFEA(F1L73Q_lut_out, STEP, !RST, , , , );


--F1L4 is control1:inst3|aluSel[1]~65
--operation mode is normal

F1L4 = F1L3 & !F1L42Q & !F1L73Q;


--F1L76 is control1:inst3|progCntrRd~1
--operation mode is normal

F1L76 = F1L96 # F1L03Q # F1L13Q # !F1L4;


--F1_addrRegWr is control1:inst3|addrRegWr
--operation mode is normal

F1_addrRegWr = F1L91Q # F1L61Q # F1L13Q # !F1L56;


--F1L41Q is control1:inst3|current_state~25
--operation mode is normal

F1L41Q_lut_out = F1L31Q;
F1L41Q = DFFEA(F1L41Q_lut_out, STEP, !RST, , , , );


--F1L92Q is control1:inst3|current_state~45
--operation mode is normal

F1L92Q_lut_out = F1L82Q;
F1L92Q = DFFEA(F1L92Q_lut_out, STEP, !RST, , , , );


--F1L33Q is control1:inst3|current_state~49
--operation mode is normal

F1L33Q_lut_out = F1L23Q;
F1L33Q = DFFEA(F1L33Q_lut_out, STEP, !RST, , , , );


--F1L19 is control1:inst3|vma~206
--operation mode is normal

F1L19 = !F1L41Q & !F1L92Q & !F1L33Q;


--M3_q[13] is reg_l:inst21|q[13]
--operation mode is normal

M3_q[13]_lut_out = A1L621;
M3_q[13] = DFFEA(M3_q[13]_lut_out, E1_inst11, !RST, , F1L43Q, , );


--YB1_q_a[13] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 16, Port B Logical Depth: 128, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_a[13]_PORT_A_data_in = A1L621;
YB1_q_a[13]_PORT_A_data_in_reg = DFFE(YB1_q_a[13]_PORT_A_data_in, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_data_in = ZB1_ram_rom_data_reg[13];
YB1_q_a[13]_PORT_B_data_in_reg = DFFE(YB1_q_a[13]_PORT_B_data_in, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[13]_PORT_A_address_reg = DFFE(YB1_q_a[13]_PORT_A_address, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[13]_PORT_B_address_reg = DFFE(YB1_q_a[13]_PORT_B_address, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_PORT_A_write_enable = F1L02Q;
YB1_q_a[13]_PORT_A_write_enable_reg = DFFE(YB1_q_a[13]_PORT_A_write_enable, YB1_q_a[13]_clock_0, , , );
YB1_q_a[13]_PORT_B_write_enable = ZB1L83;
YB1_q_a[13]_PORT_B_write_enable_reg = DFFE(YB1_q_a[13]_PORT_B_write_enable, YB1_q_a[13]_clock_1, , , );
YB1_q_a[13]_clock_0 = E1_inst11;
YB1_q_a[13]_clock_1 = A1L51;
YB1_q_a[13]_PORT_A_data_out = MEMORY(YB1_q_a[13]_PORT_A_data_in_reg, YB1_q_a[13]_PORT_B_data_in_reg, YB1_q_a[13]_PORT_A_address_reg, YB1_q_a[13]_PORT_B_address_reg, YB1_q_a[13]_PORT_A_write_enable_reg, YB1_q_a[13]_PORT_B_write_enable_reg, , , YB1_q_a[13]_clock_0, YB1_q_a[13]_clock_1, , , , );
YB1_q_a[13] = YB1_q_a[13]_PORT_A_data_out[0];

--YB1_q_b[13] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_b[13]
YB1_q_b[13]_PORT_A_data_in = A1L621;
YB1_q_b[13]_PORT_A_data_in_reg = DFFE(YB1_q_b[13]_PORT_A_data_in, YB1_q_b[13]_clock_0, , , );
YB1_q_b[13]_PORT_B_data_in = ZB1_ram_rom_data_reg[13];
YB1_q_b[13]_PORT_B_data_in_reg = DFFE(YB1_q_b[13]_PORT_B_data_in, YB1_q_b[13]_clock_1, , , );
YB1_q_b[13]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_b[13]_PORT_A_address_reg = DFFE(YB1_q_b[13]_PORT_A_address, YB1_q_b[13]_clock_0, , , );
YB1_q_b[13]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_b[13]_PORT_B_address_reg = DFFE(YB1_q_b[13]_PORT_B_address, YB1_q_b[13]_clock_1, , , );
YB1_q_b[13]_PORT_A_write_enable = F1L02Q;
YB1_q_b[13]_PORT_A_write_enable_reg = DFFE(YB1_q_b[13]_PORT_A_write_enable, YB1_q_b[13]_clock_0, , , );
YB1_q_b[13]_PORT_B_write_enable = ZB1L83;
YB1_q_b[13]_PORT_B_write_enable_reg = DFFE(YB1_q_b[13]_PORT_B_write_enable, YB1_q_b[13]_clock_1, , , );
YB1_q_b[13]_clock_0 = E1_inst11;
YB1_q_b[13]_clock_1 = A1L51;
YB1_q_b[13]_PORT_B_data_out = MEMORY(YB1_q_b[13]_PORT_A_data_in_reg, YB1_q_b[13]_PORT_B_data_in_reg, YB1_q_b[13]_PORT_A_address_reg, YB1_q_b[13]_PORT_B_address_reg, YB1_q_b[13]_PORT_A_write_enable_reg, YB1_q_b[13]_PORT_B_write_enable_reg, , , YB1_q_b[13]_clock_0, YB1_q_b[13]_clock_1, , , , );
YB1_q_b[13] = YB1_q_b[13]_PORT_B_data_out[0];


--M1_q[15] is reg_l:inst13|q[15]
--operation mode is normal

M1_q[15]_lut_out = A1L531;
M1_q[15] = DFFEA(M1_q[15]_lut_out, E1_inst8, !RST, , F1_addrRegWr, , );


--F1L71Q is control1:inst3|current_state~32
--operation mode is normal

F1L71Q_lut_out = F1L61Q;
F1L71Q = DFFEA(F1L71Q_lut_out, STEP, !RST, , , , );


--F1L29 is control1:inst3|vma~207
--operation mode is normal

F1L29 = F1L81Q # F1L24Q # F1L74Q # F1L71Q;


--F1L15Q is control1:inst3|current_state~67
--operation mode is normal

F1L15Q_lut_out = F1L05Q;
F1L15Q = DFFEA(F1L15Q_lut_out, STEP, !RST, , , , );


--F1L14Q is control1:inst3|current_state~57
--operation mode is normal

F1L14Q_lut_out = F1L04Q;
F1L14Q = DFFEA(F1L14Q_lut_out, STEP, !RST, , , , );


--F1L64Q is control1:inst3|current_state~62
--operation mode is normal

F1L64Q_lut_out = F1L54Q;
F1L64Q = DFFEA(F1L64Q_lut_out, STEP, !RST, , , , );


--F1L31Q is control1:inst3|current_state~24
--operation mode is normal

F1L31Q_lut_out = F1L21Q;
F1L31Q = DFFEA(F1L31Q_lut_out, STEP, !RST, , , , );


--F1L39 is control1:inst3|vma~208
--operation mode is normal

F1L39 = F1L15Q # F1L14Q # F1L64Q # F1L31Q;


--F1L82Q is control1:inst3|current_state~44
--operation mode is normal

F1L82Q_lut_out = F1L72Q;
F1L82Q = DFFEA(F1L82Q_lut_out, STEP, !RST, , , , );


--F1L23Q is control1:inst3|current_state~48
--operation mode is normal

F1L23Q_lut_out = F1L13Q;
F1L23Q = DFFEA(F1L23Q_lut_out, STEP, !RST, , , , );


--F1L49 is control1:inst3|vma~209
--operation mode is normal

F1L49 = F1L39 # F1L82Q # F1L23Q;


--F1L59 is control1:inst3|vma~210
--operation mode is normal

F1L59 = F1L25Q # F1L29 # F1L49 # !F1L19;


--A1L321 is gdfx_temp0[13]~1342
--operation mode is normal

A1L321 = YB1_q_a[13] & (in[13] # !M1_q[15]) # !F1L59;


--M2_q[13] is reg_l:inst17|q[13]
--operation mode is normal

M2_q[13]_lut_out = A1L621;
M2_q[13] = DFFEA(M2_q[13]_lut_out, E1_inst8, !RST, , F1L07, , );


--H1_val[13] is trireg:inst7|val[13]
--operation mode is normal

H1_val[13]_lut_out = C1L54;
H1_val[13] = DFFEA(H1_val[13]_lut_out, inst20, VCC, , , , );


--A1L421 is gdfx_temp0[13]~1343
--operation mode is normal

A1L421 = M2_q[13] & (H1_val[13] # !F1_outRegRd) # !M2_q[13] & !F1L76 & (H1_val[13] # !F1_outRegRd);


--L1_q[2] is reg:inst12|q[2]
--operation mode is normal

L1_q[2]_lut_out = A1L78;
L1_q[2] = DFFEA(L1_q[2]_lut_out, inst22, VCC, , , , );


--F1L47 is control1:inst3|reduce_or~69
--operation mode is normal

F1L47 = !F1L81Q & !F1L32Q & !F1L55Q;


--F1L68 is control1:inst3|regSel[2]~1188
--operation mode is normal

F1L68 = L1_q[2] & (F1L25Q # !F1L47 # !F1L37);


--L1_q[5] is reg:inst12|q[5]
--operation mode is normal