atd_testbench.v

来自「在硬體上將十進制轉二進制」· Verilog 代码 · 共 42 行

`timescale 1ns/1ns

module atd_testbench;

reg clk;
reg reset;
reg conv;
reg [15:0] data_in;

wire converting;
wire [15:0] digit_out;

atd atd1(
	.clk(clk),
	.reset(reset),
	.conv(conv),
	.data_in(data_in),
	.converting(converting),
	.digit_out(digit_out) 
	);
	
always #1 clk = ~clk;

initial
begin
    reset= 1;
    conv= 0;
    clk=0; 
#16 data_in= -16'd14193; 
     reset=0;
#1  conv=1;
#1  conv=0;
#32 data_in=  16'd7319;
#1  conv=1;
#1  conv=0;
#32 data_in= -16'd612;
#1  conv=1;
#1  conv=0;
#32 $stop;
end

endmodule