dist_calc.v

来自「卷积码（2」· Verilog 代码 · 共 38 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    09:52:58 07/30/09
// Design Name:    
// Module Name:    dist_calc
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module dist_calc(InputSymbol, BranchOutput, OutputDistance);
input [1:0] InputSymbol, BranchOutput; 
output [1:0] OutputDistance;
reg [1:0] OutputDistance;

wire MS, LS;

   assign MS = (InputSymbol[1] ^ BranchOutput[1]);
   assign LS = (InputSymbol[0] ^ BranchOutput[0]);

   always @(MS or LS)
   begin
      OutputDistance[1] <= MS & LS;    
      OutputDistance[0] <= MS ^ LS;    
   end

endmodule