branch_gen.v

来自「卷积码（2」· Verilog 代码 · 共 37 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    10:32:02 07/24/07
// Design Name:    
// Module Name:    branch_gen
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module branch_gen(PolyA, PolyB, BranchID, EncOut);
input [6:0] PolyA,PolyB;
input [6:0] BranchID;
output[1:0] EncOut;
reg [1:0] EncOut;

wire [6:0] wA, wB;

   assign wA = PolyA & BranchID;
   assign wB = PolyB & BranchID;

   always @(wA or wB) begin
		EncOut[1] = (((wA[0]^wA[1]) ^ (wA[2]^wA[3]))^(wA[4]^wA[5]) ^ wA[6]);
		EncOut[0] = (((wB[0]^wB[1]) ^ (wB[2]^wB[3]))^(wB[4]^wB[5]) ^ wB[6]);
   end
endmodule