dds.hier_info

用FPGA实现DDS,可变频,幅值由硬件完成

sout[1] <= cs_buffer[1].DB_MAX_OUTPUT_PORT_TYPE
sout[2] <= cs_buffer[2].DB_MAX_OUTPUT_PORT_TYPE
sout[3] <= cs_buffer[3].DB_MAX_OUTPUT_PORT_TYPE
sout[4] <= cs_buffer[4].DB_MAX_OUTPUT_PORT_TYPE
sout[5] <= cs_buffer[5].DB_MAX_OUTPUT_PORT_TYPE
sout[6] <= cs_buffer[6].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cs_buffer[0].DB_MAX_OUTPUT_PORT_TYPE
cout[1] <= cs_buffer[1].DB_MAX_OUTPUT_PORT_TYPE
cout[2] <= cs_buffer[2].DB_MAX_OUTPUT_PORT_TYPE
cout[3] <= cs_buffer[3].DB_MAX_OUTPUT_PORT_TYPE
cout[4] <= cs_buffer[4].DB_MAX_OUTPUT_PORT_TYPE
cout[5] <= cs_buffer[5].DB_MAX_OUTPUT_PORT_TYPE
cout[6] <= cs_buffer[6].DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:cout_node
sin[0] => sout_node[0].DATAIN
sin[1] => sout_node[1].DATAIN
sin[2] => sout_node[2].DATAIN
sin[3] => sout_node[3].DATAIN
sin[4] => sout_node[4].DATAIN
sin[5] => sout_node[5].DATAIN
sin[6] => sout_node[6].DATAIN
cin[0] => cout[0]~6.IN0
cin[1] => cout[1]~5.IN0
cin[2] => cout[2]~4.IN0
cin[3] => cout[3]~3.IN0
cin[4] => cout[4]~2.IN0
cin[5] => cout[5]~1.IN0
cin[6] => cout[6]~0.IN0
clk => sout_node[6].CLK
clk => sout_node[5].CLK
clk => sout_node[4].CLK
clk => sout_node[3].CLK
clk => sout_node[2].CLK
clk => sout_node[1].CLK
clk => sout_node[0].CLK
clrn => sout_node[6].ACLR
clrn => sout_node[5].ACLR
clrn => sout_node[4].ACLR
clrn => sout_node[3].ACLR
clrn => sout_node[2].ACLR
clrn => sout_node[1].ACLR
clrn => sout_node[0].ACLR
ena => sout_node[6].ENA
ena => sout_node[5].ENA
ena => sout_node[4].ENA
ena => sout_node[3].ENA
ena => sout_node[2].ENA
ena => sout_node[1].ENA
ena => sout_node[0].ENA
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
sout[1] <= sout_node[1].DB_MAX_OUTPUT_PORT_TYPE
sout[2] <= sout_node[2].DB_MAX_OUTPUT_PORT_TYPE
sout[3] <= sout_node[3].DB_MAX_OUTPUT_PORT_TYPE
sout[4] <= sout_node[4].DB_MAX_OUTPUT_PORT_TYPE
sout[5] <= sout_node[5].DB_MAX_OUTPUT_PORT_TYPE
sout[6] <= sout_node[6].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~6.DB_MAX_OUTPUT_PORT_TYPE
cout[1] <= cout[1]~5.DB_MAX_OUTPUT_PORT_TYPE
cout[2] <= cout[2]~4.DB_MAX_OUTPUT_PORT_TYPE
cout[3] <= cout[3]~3.DB_MAX_OUTPUT_PORT_TYPE
cout[4] <= cout[4]~2.DB_MAX_OUTPUT_PORT_TYPE
cout[5] <= cout[5]~1.DB_MAX_OUTPUT_PORT_TYPE
cout[6] <= cout[6]~0.DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][1]
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][0]
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][1]
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][0]
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:sign_ff[0]
d[0] => ffs[0].DATAIN
d[1] => ffs[1].DATAIN
clk => ffs[1].CLK
clk => ffs[0].CLK
clrn => ffs[1].ACLR
clrn => ffs[0].ACLR
ena => ffs[1].ENA
ena => ffs[0].ENA
q[0] <= ffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= ffs[1].DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|altshift:result_ext_latency_ffs
data[0] => result[0].DATAIN
data[1] => result[1].DATAIN
data[2] => result[2].DATAIN
data[3] => result[3].DATAIN
data[4] => result[4].DATAIN
data[5] => result[5].DATAIN
data[6] => result[6].DATAIN
data[7] => result[7].DATAIN
data[8] => result[8].DATAIN
data[9] => result[9].DATAIN
data[10] => result[10].DATAIN
data[11] => result[11].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= data[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= data[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= data[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= data[11].DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|altshift:carry_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|altshift:oflow_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|dds|bianma1:inst1
clk => kout[10]~reg0.CLK
clk => kout[9]~reg0.CLK
clk => kout[8]~reg0.CLK
clk => kout[7]~reg0.CLK
clk => kout[6]~reg0.CLK
clk => kout[5]~reg0.CLK
clk => kout[4]~reg0.CLK
clk => kout[3]~reg0.CLK
clk => kout[2]~reg0.CLK
clk => kout[1]~reg0.CLK
clk => kout[0]~reg0.CLK
clk => kout[11]~reg0.CLK
fr[0] => Mux~0.IN263
fr[0] => Mux~1.IN263
fr[0] => Mux~2.IN263
fr[0] => Mux~3.IN263
fr[0] => Mux~4.IN263
fr[0] => Mux~5.IN263
fr[0] => Mux~6.IN263
fr[0] => Mux~7.IN263
fr[1] => Mux~0.IN262
fr[1] => Mux~1.IN262
fr[1] => Mux~2.IN262
fr[1] => Mux~3.IN262
fr[1] => Mux~4.IN262
fr[1] => Mux~5.IN262
fr[1] => Mux~6.IN262
fr[1] => Mux~7.IN262
fr[2] => Mux~0.IN261
fr[2] => Mux~1.IN261
fr[2] => Mux~2.IN261
fr[2] => Mux~3.IN261
fr[2] => Mux~4.IN261
fr[2] => Mux~5.IN261
fr[2] => Mux~6.IN261
fr[2] => Mux~7.IN261
fr[3] => Mux~0.IN260
fr[3] => Mux~1.IN260
fr[3] => Mux~2.IN260
fr[3] => Mux~3.IN260
fr[3] => Mux~4.IN260
fr[3] => Mux~5.IN260
fr[3] => Mux~6.IN260
fr[3] => Mux~7.IN260
fr[4] => Mux~0.IN259
fr[4] => Mux~1.IN259
fr[4] => Mux~2.IN259
fr[4] => Mux~3.IN259
fr[4] => Mux~4.IN259
fr[4] => Mux~5.IN259
fr[4] => Mux~6.IN259
fr[4] => Mux~7.IN259
fr[5] => Mux~0.IN258
fr[5] => Mux~1.IN258
fr[5] => Mux~2.IN258
fr[5] => Mux~3.IN258
fr[5] => Mux~4.IN258
fr[5] => Mux~5.IN258
fr[5] => Mux~6.IN258
fr[5] => Mux~7.IN258
fr[6] => Mux~0.IN257
fr[6] => Mux~1.IN257
fr[6] => Mux~2.IN257
fr[6] => Mux~3.IN257
fr[6] => Mux~4.IN257
fr[6] => Mux~5.IN257
fr[6] => Mux~6.IN257
fr[6] => Mux~7.IN257
fr[7] => Mux~0.IN256
fr[7] => Mux~1.IN256
fr[7] => Mux~2.IN256
fr[7] => Mux~3.IN256
fr[7] => Mux~4.IN256
fr[7] => Mux~5.IN256
fr[7] => Mux~6.IN256
fr[7] => Mux~7.IN256
kout[0] <= kout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[1] <= kout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[2] <= kout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[3] <= kout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[4] <= kout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[5] <= kout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[6] <= kout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[7] <= kout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[8] <= kout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[9] <= kout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[10] <= kout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kout[11] <= kout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_rom1:inst9
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
address[10] => altsyncram:altsyncram_component.address_a[10]
address[11] => altsyncram:altsyncram_component.address_a[11]
clken => altsyncram:altsyncram_component.clocken0
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|lpm_rom1:inst9|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_dpu:auto_generated.address_a[0]
address_a[1] => altsyncram_dpu:auto_generated.address_a[1]
address_a[2] => altsyncram_dpu:auto_generated.address_a[2]
address_a[3] => altsyncram_dpu:auto_generated.address_a[3]
address_a[4] => altsyncram_dpu:auto_generated.address_a[4]
address_a[5] => altsyncram_dpu:auto_generated.address_a[5]
address_a[6] => altsyncram_dpu:auto_generated.address_a[6]
address_a[7] => altsyncram_dpu:auto_generated.address_a[7]
address_a[8] => altsyncram_dpu:auto_generated.address_a[8]
address_a[9] => altsyncram_dpu:auto_generated.address_a[9]
address_a[10] => altsyncram_dpu:auto_generated.address_a[10]
address_a[11] => altsyncram_dpu:auto_generated.address_a[11]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_dpu:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => altsyncram_dpu:auto_generated.clocken0
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_dpu:auto_generated.q_a[0]
q_a[1] <= altsyncram_dpu:auto_generated.q_a[1]
q_a[2] <= altsyncram_dpu:auto_generated.q_a[2]
q_a[3] <= a