dds.hier_info

用FPGA实现DDS,可变频,幅值由硬件完成

|dds
q7 <= lpm_rom1:inst.q[7]
clkin => fp:inst2.clkin
clken => lpm_rom1:inst.clken
clken => lpm_rom1:inst9.clken
fr[0] => bianma1:inst1.fr[0]
fr[1] => bianma1:inst1.fr[1]
fr[2] => bianma1:inst1.fr[2]
fr[3] => bianma1:inst1.fr[3]
fr[4] => bianma1:inst1.fr[4]
fr[5] => bianma1:inst1.fr[5]
fr[6] => bianma1:inst1.fr[6]
fr[7] => bianma1:inst1.fr[7]
q6 <= lpm_rom1:inst.q[6]
q5 <= lpm_rom1:inst.q[5]
q4 <= lpm_rom1:inst.q[4]
q3 <= lpm_rom1:inst.q[3]
q2 <= lpm_rom1:inst.q[2]
q1 <= lpm_rom1:inst.q[1]
q0 <= lpm_rom1:inst.q[0]
tt[0] <= q10.DB_MAX_OUTPUT_PORT_TYPE
tt[1] <= q11.DB_MAX_OUTPUT_PORT_TYPE
tt[2] <= q12.DB_MAX_OUTPUT_PORT_TYPE
tt[3] <= q13.DB_MAX_OUTPUT_PORT_TYPE
tt[4] <= q14.DB_MAX_OUTPUT_PORT_TYPE
tt[5] <= q15.DB_MAX_OUTPUT_PORT_TYPE
tt[6] <= q16.DB_MAX_OUTPUT_PORT_TYPE
tt[7] <= q17.DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_rom1:inst
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
address[10] => altsyncram:altsyncram_component.address_a[10]
address[11] => altsyncram:altsyncram_component.address_a[11]
clken => altsyncram:altsyncram_component.clocken0
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|lpm_rom1:inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_dpu:auto_generated.address_a[0]
address_a[1] => altsyncram_dpu:auto_generated.address_a[1]
address_a[2] => altsyncram_dpu:auto_generated.address_a[2]
address_a[3] => altsyncram_dpu:auto_generated.address_a[3]
address_a[4] => altsyncram_dpu:auto_generated.address_a[4]
address_a[5] => altsyncram_dpu:auto_generated.address_a[5]
address_a[6] => altsyncram_dpu:auto_generated.address_a[6]
address_a[7] => altsyncram_dpu:auto_generated.address_a[7]
address_a[8] => altsyncram_dpu:auto_generated.address_a[8]
address_a[9] => altsyncram_dpu:auto_generated.address_a[9]
address_a[10] => altsyncram_dpu:auto_generated.address_a[10]
address_a[11] => altsyncram_dpu:auto_generated.address_a[11]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_dpu:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => altsyncram_dpu:auto_generated.clocken0
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_dpu:auto_generated.q_a[0]
q_a[1] <= altsyncram_dpu:auto_generated.q_a[1]
q_a[2] <= altsyncram_dpu:auto_generated.q_a[2]
q_a[3] <= altsyncram_dpu:auto_generated.q_a[3]
q_a[4] <= altsyncram_dpu:auto_generated.q_a[4]
q_a[5] <= altsyncram_dpu:auto_generated.q_a[5]
q_a[6] <= altsyncram_dpu:auto_generated.q_a[6]
q_a[7] <= altsyncram_dpu:auto_generated.q_a[7]
q_b[0] <= <GND>


|dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clocken0 => ram_block1a0.ENA0
clocken0 => ram_block1a1.ENA0
clocken0 => ram_block1a2.ENA0
clocken0 => ram_block1a3.ENA0
clocken0 => ram_block1a4.ENA0
clocken0 => ram_block1a5.ENA0
clocken0 => ram_block1a6.ENA0
clocken0 => ram_block1a7.ENA0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|dds|fp:inst2
clkin => tout[6].CLK
clkin => tout[5].CLK
clkin => tout[4].CLK
clkin => tout[3].CLK
clkin => tout[2].CLK
clkin => tout[1].CLK
clkin => tout[0].CLK
clkin => cc[5].CLK
clkin => cc[4].CLK
clkin => cc[3].CLK
clkin => cc[2].CLK
clkin => cc[1].CLK
clkin => cc[0].CLK
clkin => clka.CLK
clkin => tout[7].CLK
clk <= clka.DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst4
clock => lpm_add_sub:lpm_add_sub_component.clock
dataa[0] => lpm_add_sub:lpm_add_sub_component.dataa[0]
dataa[1] => lpm_add_sub:lpm_add_sub_component.dataa[1]
dataa[2] => lpm_add_sub:lpm_add_sub_component.dataa[2]
dataa[3] => lpm_add_sub:lpm_add_sub_component.dataa[3]
dataa[4] => lpm_add_sub:lpm_add_sub_component.dataa[4]
dataa[5] => lpm_add_sub:lpm_add_sub_component.dataa[5]
dataa[6] => lpm_add_sub:lpm_add_sub_component.dataa[6]
dataa[7] => lpm_add_sub:lpm_add_sub_component.dataa[7]
dataa[8] => lpm_add_sub:lpm_add_sub_component.dataa[8]
dataa[9] => lpm_add_sub:lpm_add_sub_component.dataa[9]
dataa[10] => lpm_add_sub:lpm_add_sub_component.dataa[10]
dataa[11] => lpm_add_sub:lpm_add_sub_component.dataa[11]
datab[0] => lpm_add_sub:lpm_add_sub_component.datab[0]
datab[1] => lpm_add_sub:lpm_add_sub_component.datab[1]
datab[2] => lpm_add_sub:lpm_add_sub_component.datab[2]
datab[3] => lpm_add_sub:lpm_add_sub_component.datab[3]
datab[4] => lpm_add_sub:lpm_add_sub_component.datab[4]
datab[5] => lpm_add_sub:lpm_add_sub_component.datab[5]
datab[6] => lpm_add_sub:lpm_add_sub_component.datab[6]
datab[7] => lpm_add_sub:lpm_add_sub_component.datab[7]
datab[8] => lpm_add_sub:lpm_add_sub_component.datab[8]
datab[9] => lpm_add_sub:lpm_add_sub_component.datab[9]
datab[10] => lpm_add_sub:lpm_add_sub_component.datab[10]
datab[11] => lpm_add_sub:lpm_add_sub_component.datab[11]
result[0] <= lpm_add_sub:lpm_add_sub_component.result[0]
result[1] <= lpm_add_sub:lpm_add_sub_component.result[1]
result[2] <= lpm_add_sub:lpm_add_sub_component.result[2]
result[3] <= lpm_add_sub:lpm_add_sub_component.result[3]
result[4] <= lpm_add_sub:lpm_add_sub_component.result[4]
result[5] <= lpm_add_sub:lpm_add_sub_component.result[5]
result[6] <= lpm_add_sub:lpm_add_sub_component.result[6]
result[7] <= lpm_add_sub:lpm_add_sub_component.result[7]
result[8] <= lpm_add_sub:lpm_add_sub_component.result[8]
result[9] <= lpm_add_sub:lpm_add_sub_component.result[9]
result[10] <= lpm_add_sub:lpm_add_sub_component.result[10]
result[11] <= lpm_add_sub:lpm_add_sub_component.result[11]


|dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component
dataa[0] => addcore:adder1[0].dataa[0]
dataa[1] => addcore:adder1[0].dataa[1]
dataa[2] => addcore:adder1[0].dataa[2]
dataa[3] => addcore:adder1[0].dataa[3]
dataa[4] => addcore:adder1[0].dataa[4]
dataa[5] => addcore:adder1[0].dataa[5]
dataa[6] => addcore:adder1_0[1].dataa[0]
dataa[7] => addcore:adder1_0[1].dataa[1]
dataa[8] => addcore:adder1_0[1].dataa[2]
dataa[9] => addcore:adder1_0[1].dataa[3]
dataa[10] => addcore:adder1_0[1].dataa[4]
dataa[11] => addcore:adder1_0[1].dataa[5]
dataa[11] => bypassff:sign_ff[0].d[1]
datab[0] => addcore:adder1[0].datab[0]
datab[1] => addcore:adder1[0].datab[1]
datab[2] => addcore:adder1[0].datab[2]
datab[3] => addcore:adder1[0].datab[3]
datab[4] => addcore:adder1[0].datab[4]
datab[5] => addcore:adder1[0].datab[5]
datab[6] => addcore:adder1_0[1].datab[0]
datab[7] => addcore:adder1_0[1].datab[1]
datab[8] => addcore:adder1_0[1].datab[2]
datab[9] => addcore:adder1_0[1].datab[3]
datab[10] => addcore:adder1_0[1].datab[4]
datab[11] => addcore:adder1_0[1].datab[5]
datab[11] => bypassff:sign_ff[0].d[0]
cin => ~NO_FANOUT~
add_sub => cin_node.IN0
clock => addcore:adder1[0].clock
clock => addcore:adder1_0[1].clock
clock => bypassff:sign_ff[0].clk
aclr => addcore:adder1[0].aclr
aclr => addcore:adder1_0[1].aclr
clken => addcore:adder1[0].clken
clken => addcore:adder1_0[1].clken
clken => bypassff:sign_ff[0].ena
result[0] <= altshift:result_ext_latency_ffs.result[0]
result[1] <= altshift:result_ext_latency_ffs.result[1]
result[2] <= altshift:result_ext_latency_ffs.result[2]
result[3] <= altshift:result_ext_latency_ffs.result[3]
result[4] <= altshift:result_ext_latency_ffs.result[4]
result[5] <= altshift:result_ext_latency_ffs.result[5]
result[6] <= altshift:result_ext_latency_ffs.result[6]
result[7] <= altshift:result_ext_latency_ffs.result[7]
result[8] <= altshift:result_ext_latency_ffs.result[8]
result[9] <= altshift:result_ext_latency_ffs.result[9]
result[10] <= altshift:result_ext_latency_ffs.result[10]
result[11] <= altshift:result_ext_latency_ffs.result[11]
cout <= cout~0.DB_MAX_OUTPUT_PORT_TYPE
overflow <= overflow~0.DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
datab[2] => datab_node[2].IN0
datab[3] => datab_node[3].IN0
datab[4] => datab_node[4].IN0
datab[5] => datab_node[5].IN0
datab[6] => datab_node[6].IN0
cin => ~NO_FANOUT~
add_sub => cin_node.IN0
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= a_csnbuffer:result_node.sout[0]
result[1] <= a_csnbuffer:result_node.sout[1]
result[2] <= a_csnbuffer:result_node.sout[2]
result[3] <= a_csnbuffer:result_node.sout[3]
result[4] <= a_csnbuffer:result_node.sout[4]
result[5] <= a_csnbuffer:result_node.sout[5]
result[6] <= a_csnbuffer:result_node.sout[6]
cout <= a_csnbuffer:cout_node.sout[0]
unreg_result[0] <= unreg_res_node[0].DB_MAX_OUTPUT_PORT_TYPE
unreg_result[1] <= unreg_res_node[1].DB_MAX_OUTPUT_PORT_TYPE
unreg_result[2] <= unreg_res_node[2].DB_MAX_OUTPUT_PORT_TYPE
unreg_result[3] <= unreg_res_node[3].DB_MAX_OUTPUT_PORT_TYPE
unreg_result[4] <= unreg_res_node[4].DB_MAX_OUTPUT_PORT_TYPE
unreg_result[5] <= unreg_res_node[5].DB_MAX_OUTPUT_PORT_TYPE
unreg_result[6] <= unreg_res_node[6].DB_MAX_OUTPUT_PORT_TYPE
unreg_cout <= unreg_cout_node.DB_MAX_OUTPUT_PORT_TYPE