dds.hif

用FPGA实现DDS,可变频,幅值由硬件完成

PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
cin
-1
3
aclr
-1
3
}
# include_file {
e:|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
e:|altera|quartus51|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
e:|altera|quartus51|libraries|megafunctions|a_csnbuffer.inc
49de46f6a395e2e6edecabe6eac9d873
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]
}
# end
# entity
a_csnbuffer
# storage
db|dds.(11).cnf
db|dds.(11).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|a_csnbuffer.tdf
14fa1fe880ca66e7782a2fafd457197
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
NEED_CARRY
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout6
-1
3
sout5
-1
3
sout4
-1
3
sout3
-1
3
sout2
-1
3
sout1
-1
3
sout0
-1
3
sin6
-1
3
sin5
-1
3
sin4
-1
3
sin3
-1
3
sin2
-1
3
sin1
-1
3
sin0
-1
3
ena
-1
3
cout6
-1
3
cout5
-1
3
cout4
-1
3
cout3
-1
3
cout2
-1
3
cout1
-1
3
cout0
-1
3
clrn
-1
3
clk
-1
3
cin6
-1
3
cin5
-1
3
cin4
-1
3
cin3
-1
3
cin2
-1
3
cin1
-1
3
cin0
-1
3
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node
}
# end
# entity
a_csnbuffer
# storage
db|dds.(12).cnf
db|dds.(12).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|a_csnbuffer.tdf
14fa1fe880ca66e7782a2fafd457197
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout0
-1
3
sin0
-1
3
ena
-1
3
clrn
-1
3
clk
-1
3
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:cout_node
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:cout_node
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:cout_node
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:cout_node
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:cout_node
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:cout_node
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:cout_node
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:cout_node
}
# end
# entity
addcore
# storage
db|dds.(13).cnf
db|dds.(13).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|addcore.tdf
dacc8d7ac3d13616838bdd54be6656bf
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
7
PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# include_file {
e:|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
e:|altera|quartus51|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
e:|altera|quartus51|libraries|megafunctions|a_csnbuffer.inc
49de46f6a395e2e6edecabe6eac9d873
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]
}
# end
# entity
bypassff
# storage
db|dds.(14).cnf
db|dds.(14).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|bypassff.tdf
ca2b1078a9dd3b6b4f1a640b57c24be
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
}
# used_port {
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][1]
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][0]
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][1]
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][0]
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][1]
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][0]
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][1]
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][0]
}
# end
# entity
bypassff
# storage
db|dds.(15).cnf
db|dds.(15).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|bypassff.tdf
ca2b1078a9dd3b6b4f1a640b57c24be
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
}
# used_port {
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][1]
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][0]
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][1]
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][0]
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][1]
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][0]
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][1]
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][0]
}
# end
# entity
bypassff
# storage
db|dds.(16).cnf
db|dds.(16).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|bypassff.tdf
ca2b1078a9dd3b6b4f1a640b57c24be
6
# user_parameter {
WIDTH
2
PARAMETER_UNKNOWN
USR
}
# used_port {
q1
-1
3
q0
-1
3
ena
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clk
-1
3
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|bypassff:sign_ff[0]
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|bypassff:sign_ff[0]
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|bypassff:sign_ff[0]
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|bypassff:sign_ff[0]
}
# end
# entity
altshift
# storage
db|dds.(17).cnf
db|dds.(17).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|altshift.tdf
2ae786dd85a23b221e99d5553e5caf5
6
# user_parameter {
WIDTH
12
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|altshift:result_ext_latency_ffs
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|altshift:result_ext_latency_ffs
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|altshift:result_ext_latency_ffs
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|altshift:result_ext_latency_ffs
}
# end
# entity
altshift
# storage
db|dds.(18).cnf
db|dds.(18).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|altshift.tdf
2ae786dd85a23b221e99d5553e5caf5
6
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
result0
-1
3
data0
-1
3
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|altshift:carry_ext_latency_ffs
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|altshift:oflow_ext_latency_ffs
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|altshift:carry_ext_latency_ffs
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|altshift:oflow_ext_latency_ffs
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|altshift:carry_ext_latency_ffs
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|altshift:oflow_ext_latency_ffs
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|altshift:carry_ext_latency_ffs
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|altshift:oflow_ext_latency_ffs
}
# end
# entity
altsyncram
# storage
db|dds.(21).cnf
db|dds.(21).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|altsyncram.tdf
2e50408acd947bab10aa53249c64526
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
12
PARAMETER_DEC
USR
NUMWORDS_A
4096
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
C:/Documents and Settings/ryu/桌面/Mif1.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_f9v
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clocken0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1