dds.hif

用FPGA实现DDS,可变频,幅值由硬件完成

Version 5.1 Build 176 10/26/2005 SJ Full Version
33
1707
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
lpm_rom0
# storage
db|dds.(1).cnf
db|dds.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpm_rom0.vhd
40d678cf3e5ce15aa272a833303db6cb
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
altsyncram
# storage
db|dds.(2).cnf
db|dds.(2).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|altsyncram.tdf
2e50408acd947bab10aa53249c64526
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
12
PARAMETER_DEC
USR
NUMWORDS_A
4096
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
D:/Mif1.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_dqs
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clocken0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
e:|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
e:|altera|quartus51|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
e:|altera|quartus51|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
e:|altera|quartus51|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
e:|altera|quartus51|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
e:|altera|quartus51|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
e:|altera|quartus51|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
e:|altera|quartus51|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
e:|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
e:|altera|quartus51|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_dqs
# storage
db|dds.(3).cnf
db|dds.(3).cnf
# case_insensitive
# source_file
db|altsyncram_dqs.tdf
7f5f9c55e4ed4c3576f79abf551ac9b
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clocken0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
D:|Mif1.mif
0
}
# end
# entity
lpm_add_sub2
# storage
db|dds.(5).cnf
db|dds.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpm_add_sub2.vhd
19b691b07a31ca984224da57845db95
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
lpm_add_sub2:inst4
lpm_add_sub2:inst3
lpm_add_sub2:inst6
lpm_add_sub2:inst5
}
# end
# entity
lpm_add_sub
# storage
db|dds.(6).cnf
db|dds.(6).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|lpm_add_sub.tdf
6d69e5f6592ac38b99b31695315abe8
6
# user_parameter {
LPM_WIDTH
12
PARAMETER_DEC
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_4fg
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
}
# include_file {
e:|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
e:|altera|quartus51|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
e:|altera|quartus51|libraries|megafunctions|look_add.inc
ab9f577d30c5ef3166fab6c1c32c4a
e:|altera|quartus51|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
e:|altera|quartus51|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
e:|altera|quartus51|libraries|megafunctions|alt_stratix_add_sub.inc
c08f604aefba5b4f1f554e565113c6
e:|altera|quartus51|libraries|megafunctions|alt_mercury_add_sub.inc
ae39f15ed67cc9a095d29f68f6ad0f8
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component
}
# end
# entity
addcore
# storage
db|dds.(7).cnf
db|dds.(7).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|addcore.tdf
dacc8d7ac3d13616838bdd54be6656bf
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
7
PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
unreg_result5
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa0
-1
3
}
# include_file {
e:|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
e:|altera|quartus51|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
e:|altera|quartus51|libraries|megafunctions|a_csnbuffer.inc
49de46f6a395e2e6edecabe6eac9d873
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]
}
# end
# entity
a_csnbuffer
# storage
db|dds.(8).cnf
db|dds.(8).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|a_csnbuffer.tdf
14fa1fe880ca66e7782a2fafd457197
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout0
-1
3
sin0
-1
3
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:oflow_node
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:cout_node
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:oflow_node
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:oflow_node
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:oflow_node
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:cout_node
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:oflow_node
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:oflow_node
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:oflow_node
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:cout_node
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:oflow_node
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:oflow_node
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:oflow_node
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:cout_node
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:oflow_node
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:oflow_node
}
# end
# entity
a_csnbuffer
# storage
db|dds.(9).cnf
db|dds.(9).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|a_csnbuffer.tdf
14fa1fe880ca66e7782a2fafd457197
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
NEED_CARRY
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout6
-1
3
sout5
-1
3
sout4
-1
3
sout3
-1
3
sout2
-1
3
sout1
-1
3
sout0
-1
3
sin6
-1
3
sin5
-1
3
sin4
-1
3
sin3
-1
3
sin2
-1
3
sin1
-1
3
sin0
-1
3
cout6
-1
3
cout5
-1
3
cout4
-1
3
cout3
-1
3
cout2
-1
3
cout1
-1
3
cout0
-1
3
cin6
-1
3
cin5
-1
3
cin4
-1
3
cin3
-1
3
cin2
-1
3
cin1
-1
3
cin0
-1
3
}
# hierarchies {
lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node
lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node
lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node
lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node
}
# end
# entity
addcore
# storage
db|dds.(10).cnf
db|dds.(10).cnf
# case_insensitive
# source_file
e:|altera|quartus51|libraries|megafunctions|addcore.tdf
dacc8d7ac3d13616838bdd54be6656bf
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
7