dds.map.qmsg

用FPGA实现DDS,可变频,幅值由硬件完成

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\] " "Info: Elaborating entity \"addcore\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\"" {  } { { "lpm_add_sub.tdf" "adder1\[0\]" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 240 11 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:cout_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:cout_node\"" {  } { { "addcore.tdf" "cout_node" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 122 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\] " "Info: Elaborating entity \"addcore\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\"" {  } { { "lpm_add_sub.tdf" "adder1_0\[1\]" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 245 14 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/bypassff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/bypassff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 bypassff " "Info: Found entity 1: bypassff" {  } { { "bypassff.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/bypassff.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bypassff lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[1\]\[1\] " "Info: Elaborating entity \"bypassff\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[1\]\[1\]\"" {  } { { "lpm_add_sub.tdf" "datab1_ff\[1\]\[1\]" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 251 13 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bypassff lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[0\]\[1\] " "Info: Elaborating entity \"bypassff\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[0\]\[1\]\"" {  } { { "lpm_add_sub.tdf" "datab1_ff\[0\]\[1\]" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 251 13 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bypassff lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|bypassff:sign_ff\[0\] " "Info: Elaborating entity \"bypassff\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|bypassff:sign_ff\[0\]\"" {  } { { "lpm_add_sub.tdf" "sign_ff\[0\]" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 254 12 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|altshift:result_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|altshift:result_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "result_ext_latency_ffs" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|altshift:carry_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|altshift:carry_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "carry_ext_latency_ffs" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bianma1 bianma1:inst1 " "Info: Elaborating entity \"bianma1\" for hierarchy \"bianma1:inst1\"" {  } { { "dds.bdf" "inst1" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { 152 152 296 248 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bianma1:inst1\|kout\[10\] data_in GND " "Warning: Reduced register \"bianma1:inst1\|kout\[10\]\" with stuck data_in port to stuck value GND" {  } { { "bianma1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/bianma1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bianma1:inst1\|kout\[9\] data_in GND " "Warning: Reduced register \"bianma1:inst1\|kout\[9\]\" with stuck data_in port to stuck value GND" {  } { { "bianma1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/bianma1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bianma1:inst1\|kout\[8\] data_in GND " "Warning: Reduced register \"bianma1:inst1\|kout\[8\]\" with stuck data_in port to stuck value GND" {  } { { "bianma1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/bianma1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bianma1:inst1\|kout\[11\] data_in GND " "Warning: Reduced register \"bianma1:inst1\|kout\[11\]\" with stuck data_in port to stuck value GND" {  } { { "bianma1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/bianma1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\] data_in GND " "Warning: Reduced register \"lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\]\" with stuck data_in port to stuck value GND" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\] data_in GND " "Warning: Reduced register \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\]\" with stuck data_in port to stuck value GND" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\] lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\] " "Info: Duplicate register \"lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\]\" merged to single register \"lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\]\"" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[4\] lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[4\] " "Info: Duplicate register \"lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[4\]\" merged to single register \"lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[4\]\"" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\] lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\] " "Info: Duplicate register \"lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]\" merged to single register \"lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]\"" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\] lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\] " "Info: Duplicate register \"lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\]\" merged to single register \"lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\]\"" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\] lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\] " "Info: Duplicate register \"lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]\" merged to single register \"lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]\"" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\] lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\] " "Info: Duplicate register \"lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]\" merged to single register \"lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]\"" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[0\] lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[0\] " "Info: Duplicate register \"lpm_add_sub2:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[0\]\" merged to single register \"lpm_add_sub2:inst5\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[0\]\", power-up level changed" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "bianma1:inst1\|Mux~2048 256 8 " "Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=8) from the following design logic: \"bianma1:inst1\|Mux~2048\"" {  } {  } 0 0 "Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_btk.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_btk.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_btk " "Info: Found entity 1: altsyncram_btk" {  } { { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "1 " "Info: Ignored 1 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "1 " "Info: Ignored 1 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "134 " "Info: Implemented 134 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "84 " "Info: Implemented 84 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "24 " "Info: Implemented 24 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 30 13:12:34 2007 " "Info: Processing ended: Mon Jul 30 13:12:34 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}