dds.map.qmsg

用FPGA实现DDS,可变频,幅值由硬件完成

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 30 13:12:30 2007 " "Info: Processing started: Mon Jul 30 13:12:30 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bianma1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bianma1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bianma1-aaa " "Info: Found design unit 1: bianma1-aaa" {  } { { "bianma1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/bianma1.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bianma1 " "Info: Found entity 1: bianma1" {  } { { "bianma1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/bianma1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../fp/Vhdl1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../fp/Vhdl1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fp-a " "Info: Found design unit 1: fp-a" {  } { { "../fp/Vhdl1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/fp/Vhdl1.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fp " "Info: Found entity 1: fp" {  } { { "../fp/Vhdl1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/fp/Vhdl1.vhd" 30 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { 344 968 1144 360 "q\[7..0\]" "" } { 344 968 1144 360 "q\[7..0\]" "" } { 344 968 1144 360 "q\[7..0\]" "" } { 344 968 1144 360 "q\[7..0\]" "" } { 344 968 1144 360 "q\[7..0\]" "" } { 344 968 1144 360 "q\[7..0\]" "" } { 344 968 1144 360 "q\[7..0\]" "" } { 344 968 1144 360 "q\[7..0\]" "" } { 344 968 1144 360 "q\[7..0\]" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { -192 1144 1208 -176 "q1\[7..0\]" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom1.vhd 2 1 " "Warning: Using design file lpm_rom1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom1-SYN " "Info: Found design unit 1: lpm_rom1-SYN" {  } { { "lpm_rom1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/lpm_rom1.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom1 " "Info: Found entity 1: lpm_rom1" {  } { { "lpm_rom1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/lpm_rom1.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom1 lpm_rom1:inst " "Info: Elaborating entity \"lpm_rom1\" for hierarchy \"lpm_rom1:inst\"" {  } { { "dds.bdf" "inst" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { 376 880 1040 472 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom1:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom1:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom1.vhd" "altsyncram_component" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/lpm_rom1.vhd" 82 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dpu.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_dpu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dpu " "Info: Found entity 1: altsyncram_dpu" {  } { { "db/altsyncram_dpu.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_dpu.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_dpu lpm_rom1:inst\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated " "Info: Elaborating entity \"altsyncram_dpu\" for hierarchy \"lpm_rom1:inst\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp fp:inst2 " "Info: Elaborating entity \"fp\" for hierarchy \"fp:inst2\"" {  } { { "dds.bdf" "inst2" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { 40 328 424 136 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clka Vhdl1.vhd(72) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(72): signal \"clka\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "../fp/Vhdl1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/fp/Vhdl1.vhd" 72 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_add_sub2.vhd 2 1 " "Warning: Using design file lpm_add_sub2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_add_sub2-SYN " "Info: Found design unit 1: lpm_add_sub2-SYN" {  } { { "lpm_add_sub2.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/lpm_add_sub2.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub2 " "Info: Found entity 1: lpm_add_sub2" {  } { { "lpm_add_sub2.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/lpm_add_sub2.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub2 lpm_add_sub2:inst4 " "Info: Elaborating entity \"lpm_add_sub2\" for hierarchy \"lpm_add_sub2:inst4\"" {  } { { "dds.bdf" "inst4" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { 360 408 568 456 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub2.vhd" "lpm_add_sub_component" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/lpm_add_sub2.vhd" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\] " "Info: Elaborating entity \"addcore\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\"" {  } { { "lpm_add_sub.tdf" "adder1\[1\]" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 240 11 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:oflow_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:oflow_node\"" {  } { { "addcore.tdf" "oflow_node" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 94 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"lpm_add_sub2:inst4\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}