dds.tan.qmsg

用FPGA实现DDS,可变频,幅值由硬件完成

{ "Info" "ITDB_TSU_RESULT" "lpm_rom1:inst9\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[7\] clken clkin 3.229 ns memory " "Info: tsu for memory \"lpm_rom1:inst9\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[7\]\" (data pin = \"clken\", clock pin = \"clkin\") is 3.229 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.003 ns + Longest pin memory " "Info: + Longest pin to memory delay is 11.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clken 1 PIN PIN_159 208 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_159; Fanout = 208; PIN Node = 'clken'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { clken } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { -8 -88 80 8 "clken" "" } { -176 912 984 -160 "clken" "" } { 424 824 880 440 "clken" "" } { -16 80 128 0 "clken" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.583 ns) + CELL(0.951 ns) 11.003 ns lpm_rom1:inst9\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[7\] 2 MEM M4K_X17_Y2 1 " "Info: 2: + IC(8.583 ns) + CELL(0.951 ns) = 11.003 ns; Loc. = M4K_X17_Y2; Fanout = 1; MEM Node = 'lpm_rom1:inst9\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[7\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "9.534 ns" { clken lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "db/altsyncram_dpu.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_dpu.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.420 ns ( 21.99 % ) " "Info: Total cell delay = 2.420 ns ( 21.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.583 ns ( 78.01 % ) " "Info: Total interconnect delay = 8.583 ns ( 78.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "11.003 ns" { clken lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "11.003 ns" { clken clken~out0 lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } { 0.000ns 0.000ns 8.583ns } { 0.000ns 1.469ns 0.951ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_dpu.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_dpu.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 7.867 ns - Shortest memory " "Info: - Shortest clock path from clock \"clkin\" to destination memory is 7.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clkin'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { clkin } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { -24 208 376 -8 "clkin" "" } { -32 376 464 -16 "clkin" "" } { 56 264 328 72 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns fp:inst2\|clka 2 REG LC_X8_Y7_N2 260 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X8_Y7_N2; Fanout = 260; REG Node = 'fp:inst2\|clka'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "1.658 ns" { clkin fp:inst2|clka } "NODE_NAME" } "" } } { "../fp/Vhdl1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/fp/Vhdl1.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.032 ns) + CELL(0.708 ns) 7.867 ns lpm_rom1:inst9\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[7\] 3 MEM M4K_X17_Y2 1 " "Info: 3: + IC(4.032 ns) + CELL(0.708 ns) = 7.867 ns; Loc. = M4K_X17_Y2; Fanout = 1; MEM Node = 'lpm_rom1:inst9\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[7\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "4.740 ns" { fp:inst2|clka lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "db/altsyncram_dpu.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_dpu.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.112 ns ( 39.56 % ) " "Info: Total cell delay = 3.112 ns ( 39.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.755 ns ( 60.44 % ) " "Info: Total interconnect delay = 4.755 ns ( 60.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.867 ns" { clkin fp:inst2|clka lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.867 ns" { clkin clkin~out0 fp:inst2|clka lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } { 0.000ns 0.000ns 0.723ns 4.032ns } { 0.000ns 1.469ns 0.935ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "11.003 ns" { clken lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "11.003 ns" { clken clken~out0 lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } { 0.000ns 0.000ns 8.583ns } { 0.000ns 1.469ns 0.951ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.867 ns" { clkin fp:inst2|clka lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.867 ns" { clkin clkin~out0 fp:inst2|clka lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7] } { 0.000ns 0.000ns 0.723ns 4.032ns } { 0.000ns 1.469ns 0.935ns 0.708ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin q0 lpm_rom1:inst\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[0\] 13.947 ns memory " "Info: tco from clock \"clkin\" to destination pin \"q0\" through memory \"lpm_rom1:inst\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[0\]\" is 13.947 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 7.896 ns + Longest memory " "Info: + Longest clock path from clock \"clkin\" to source memory is 7.896 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clkin'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { clkin } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { -24 208 376 -8 "clkin" "" } { -32 376 464 -16 "clkin" "" } { 56 264 328 72 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns fp:inst2\|clka 2 REG LC_X8_Y7_N2 260 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X8_Y7_N2; Fanout = 260; REG Node = 'fp:inst2\|clka'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "1.658 ns" { clkin fp:inst2|clka } "NODE_NAME" } "" } } { "../fp/Vhdl1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/fp/Vhdl1.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.061 ns) + CELL(0.708 ns) 7.896 ns lpm_rom1:inst\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[0\] 3 MEM M4K_X17_Y10 1 " "Info: 3: + IC(4.061 ns) + CELL(0.708 ns) = 7.896 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'lpm_rom1:inst\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "4.769 ns" { fp:inst2|clka lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] } "NODE_NAME" } "" } } { "db/altsyncram_dpu.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_dpu.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.112 ns ( 39.41 % ) " "Info: Total cell delay = 3.112 ns ( 39.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.784 ns ( 60.59 % ) " "Info: Total interconnect delay = 4.784 ns ( 60.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.896 ns" { clkin fp:inst2|clka lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.896 ns" { clkin clkin~out0 fp:inst2|clka lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.723ns 4.061ns } { 0.000ns 1.469ns 0.935ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_dpu.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_dpu.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.401 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.401 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns lpm_rom1:inst\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[0\] 1 MEM M4K_X17_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'lpm_rom1:inst\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] } "NODE_NAME" } "" } } { "db/altsyncram_dpu.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_dpu.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.189 ns) + CELL(2.108 ns) 5.401 ns q0 2 PIN PIN_188 0 " "Info: 2: + IC(3.189 ns) + CELL(2.108 ns) = 5.401 ns; Loc. = PIN_188; Fanout = 0; PIN Node = 'q0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "5.297 ns" { lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] q0 } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { 344 968 1144 360 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns ( 40.96 % ) " "Info: Total cell delay = 2.212 ns ( 40.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.189 ns ( 59.04 % ) " "Info: Total interconnect delay = 3.189 ns ( 59.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "5.401 ns" { lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] q0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.401 ns" { lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] q0 } { 0.000ns 3.189ns } { 0.104ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.896 ns" { clkin fp:inst2|clka lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.896 ns" { clkin clkin~out0 fp:inst2|clka lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.723ns 4.061ns } { 0.000ns 1.469ns 0.935ns 0.708ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "5.401 ns" { lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] q0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.401 ns" { lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0] q0 } { 0.000ns 3.189ns } { 0.104ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg4 fr\[4\] clkin -0.473 ns memory " "Info: th for memory \"bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg4\" (data pin = \"fr\[4\]\", clock pin = \"clkin\") is -0.473 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 7.910 ns + Longest memory " "Info: + Longest clock path from clock \"clkin\" to destination memory is 7.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clkin'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { clkin } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { -24 208 376 -8 "clkin" "" } { -32 376 464 -16 "clkin" "" } { 56 264 328 72 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns fp:inst2\|clka 2 REG LC_X8_Y7_N2 260 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X8_Y7_N2; Fanout = 260; REG Node = 'fp:inst2\|clka'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "1.658 ns" { clkin fp:inst2|clka } "NODE_NAME" } "" } } { "../fp/Vhdl1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/fp/Vhdl1.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.061 ns) + CELL(0.722 ns) 7.910 ns bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg4 3 MEM M4K_X17_Y12 8 " "Info: 3: + IC(4.061 ns) + CELL(0.722 ns) = 7.910 ns; Loc. = M4K_X17_Y12; Fanout = 8; MEM Node = 'bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg4'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "4.783 ns" { fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 169 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns ( 39.52 % ) " "Info: Total cell delay = 3.126 ns ( 39.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.784 ns ( 60.48 % ) " "Info: Total interconnect delay = 4.784 ns ( 60.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.910 ns" { clkin fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.910 ns" { clkin clkin~out0 fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } { 0.000ns 0.000ns 0.723ns 4.061ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.055 ns + " "Info: + Micro hold delay of destination is 0.055 ns" {  } { { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 169 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.438 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 8.438 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fr\[4\] 1 PIN PIN_162 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_162; Fanout = 1; PIN Node = 'fr\[4\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { fr[4] } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { 184 -200 -32 200 "fr\[7..0\]" "" } { 184 96 152 200 "fr\[7..0\]" "" } { 176 -32 16 192 "fr\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.586 ns) + CELL(0.383 ns) 8.438 ns bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg4 2 MEM M4K_X17_Y12 8 " "Info: 2: + IC(6.586 ns) + CELL(0.383 ns) = 8.438 ns; Loc. = M4K_X17_Y12; Fanout = 8; MEM Node = 'bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg4'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "6.969 ns" { fr[4] bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 169 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.852 ns ( 21.95 % ) " "Info: Total cell delay = 1.852 ns ( 21.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.586 ns ( 78.05 % ) " "Info: Total interconnect delay = 6.586 ns ( 78.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "8.438 ns" { fr[4] bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "8.438 ns" { fr[4] fr[4]~out0 bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } { 0.000ns 0.000ns 6.586ns } { 0.000ns 1.469ns 0.383ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.910 ns" { clkin fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.910 ns" { clkin clkin~out0 fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } { 0.000ns 0.000ns 0.723ns 4.061ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "8.438 ns" { fr[4] bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "8.438 ns" { fr[4] fr[4]~out0 bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4 } { 0.000ns 0.000ns 6.586ns } { 0.000ns 1.469ns 0.383ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}