dds.tan.qmsg

用FPGA实现DDS,可变频,幅值由硬件完成

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { -24 208 376 -8 "clkin" "" } { -32 376 464 -16 "clkin" "" } { 56 264 328 72 "clkin" "" } } } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fp:inst2\|clka " "Info: Detected ripple clock \"fp:inst2\|clka\" as buffer" {  } { { "../fp/Vhdl1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/fp/Vhdl1.vhd" 53 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fp:inst2\|clka" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin memory bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg0 register lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\] 116.39 MHz 8.592 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 116.39 MHz between source memory \"bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg0\" and destination register \"lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\]\" (period= 8.592 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.856 ns + Longest memory register " "Info: + Longest memory to register delay is 7.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg0 1 MEM M4K_X17_Y12 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y12; Fanout = 8; MEM Node = 'bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 169 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|q_a\[1\] 2 MEM M4K_X17_Y12 3 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y12; Fanout = 3; MEM Node = 'bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|q_a\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "4.308 ns" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.952 ns) + CELL(0.423 ns) 6.683 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]~43 3 COMB LC_X14_Y7_N1 2 " "Info: 3: + IC(1.952 ns) + CELL(0.423 ns) = 6.683 ns; Loc. = LC_X14_Y7_N1; Fanout = 2; COMB Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]~43'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "2.375 ns" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 6.761 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]~47 4 COMB LC_X14_Y7_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 6.761 ns; Loc. = LC_X14_Y7_N2; Fanout = 2; COMB Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]~47'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "0.078 ns" { lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 6.839 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\]~51 5 COMB LC_X14_Y7_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 6.839 ns; Loc. = LC_X14_Y7_N3; Fanout = 2; COMB Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\]~51'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "0.078 ns" { lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 7.017 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]~55 6 COMB LC_X14_Y7_N4 2 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 7.017 ns; Loc. = LC_X14_Y7_N4; Fanout = 2; COMB Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]~55'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "0.178 ns" { lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 7.856 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\] 7 REG LC_X14_Y7_N6 2 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 7.856 ns; Loc. = LC_X14_Y7_N6; Fanout = 2; REG Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "0.839 ns" { lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.904 ns ( 75.15 % ) " "Info: Total cell delay = 5.904 ns ( 75.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.952 ns ( 24.85 % ) " "Info: Total interconnect delay = 1.952 ns ( 24.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.856 ns" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.856 ns" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } { 0.000ns 0.000ns 1.952ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 4.308ns 0.423ns 0.078ns 0.078ns 0.178ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.049 ns - Smallest " "Info: - Smallest clock skew is -0.049 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 7.861 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 7.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clkin'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { clkin } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { -24 208 376 -8 "clkin" "" } { -32 376 464 -16 "clkin" "" } { 56 264 328 72 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns fp:inst2\|clka 2 REG LC_X8_Y7_N2 260 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X8_Y7_N2; Fanout = 260; REG Node = 'fp:inst2\|clka'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "1.658 ns" { clkin fp:inst2|clka } "NODE_NAME" } "" } } { "../fp/Vhdl1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/fp/Vhdl1.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.023 ns) + CELL(0.711 ns) 7.861 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\] 3 REG LC_X14_Y7_N6 2 " "Info: 3: + IC(4.023 ns) + CELL(0.711 ns) = 7.861 ns; Loc. = LC_X14_Y7_N6; Fanout = 2; REG Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[5\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "4.734 ns" { fp:inst2|clka lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.63 % ) " "Info: Total cell delay = 3.115 ns ( 39.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.746 ns ( 60.37 % ) " "Info: Total interconnect delay = 4.746 ns ( 60.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.861 ns" { clkin fp:inst2|clka lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.861 ns" { clkin clkin~out0 fp:inst2|clka lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } { 0.000ns 0.000ns 0.723ns 4.023ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 7.910 ns - Longest memory " "Info: - Longest clock path from clock \"clkin\" to source memory is 7.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clkin'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { clkin } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.bdf" { { -24 208 376 -8 "clkin" "" } { -32 376 464 -16 "clkin" "" } { 56 264 328 72 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns fp:inst2\|clka 2 REG LC_X8_Y7_N2 260 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X8_Y7_N2; Fanout = 260; REG Node = 'fp:inst2\|clka'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "1.658 ns" { clkin fp:inst2|clka } "NODE_NAME" } "" } } { "../fp/Vhdl1.vhd" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/fp/Vhdl1.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.061 ns) + CELL(0.722 ns) 7.910 ns bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg0 3 MEM M4K_X17_Y12 8 " "Info: 3: + IC(4.061 ns) + CELL(0.722 ns) = 7.910 ns; Loc. = M4K_X17_Y12; Fanout = 8; MEM Node = 'bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "4.783 ns" { fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 169 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns ( 39.52 % ) " "Info: Total cell delay = 3.126 ns ( 39.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.784 ns ( 60.48 % ) " "Info: Total interconnect delay = 4.784 ns ( 60.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.910 ns" { clkin fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.910 ns" { clkin clkin~out0 fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.723ns 4.061ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.861 ns" { clkin fp:inst2|clka lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.861 ns" { clkin clkin~out0 fp:inst2|clka lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } { 0.000ns 0.000ns 0.723ns 4.023ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.910 ns" { clkin fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.910 ns" { clkin clkin~out0 fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.723ns 4.061ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 169 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.856 ns" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.856 ns" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } { 0.000ns 0.000ns 1.952ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 4.308ns 0.423ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.861 ns" { clkin fp:inst2|clka lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.861 ns" { clkin clkin~out0 fp:inst2|clka lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] } { 0.000ns 0.000ns 0.723ns 4.023ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "7.910 ns" { clkin fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.910 ns" { clkin clkin~out0 fp:inst2|clka bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.723ns 4.061ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}