dds.fit.qmsg

用FPGA实现DDS,可变频,幅值由硬件完成

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.058 ns memory register " "Info: Estimated most critical path is memory to register delay of 8.058 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a1~porta_address_reg0 1 MEM M4K_X17_Y12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y12; Fanout = 1; MEM Node = 'bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|ram_block1a1~porta_address_reg0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 61 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|q_a\[1\] 2 MEM M4K_X17_Y12 3 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y12; Fanout = 3; MEM Node = 'bianma1:inst1\|altsyncram:Mux_rtl_0\|altsyncram_btk:auto_generated\|q_a\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "4.308 ns" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a1~porta_address_reg0 bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "db/altsyncram_btk.tdf" "" { Text "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/altsyncram_btk.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.859 ns) + CELL(0.575 ns) 6.742 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]~43COUT1_67 3 COMB LAB_X14_Y7 2 " "Info: 3: + IC(1.859 ns) + CELL(0.575 ns) = 6.742 ns; Loc. = LAB_X14_Y7; Fanout = 2; COMB Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]~43COUT1_67'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "2.434 ns" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43COUT1_67 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.822 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]~47COUT1_68 4 COMB LAB_X14_Y7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 6.822 ns; Loc. = LAB_X14_Y7; Fanout = 2; COMB Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]~47COUT1_68'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "0.080 ns" { lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43COUT1_67 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47COUT1_68 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.902 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\]~51COUT1 5 COMB LAB_X14_Y7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 6.902 ns; Loc. = LAB_X14_Y7; Fanout = 2; COMB Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[2\]~51COUT1'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "0.080 ns" { lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47COUT1_68 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51COUT1 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 7.160 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]~55 6 COMB LAB_X14_Y7 2 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 7.160 ns; Loc. = LAB_X14_Y7; Fanout = 2; COMB Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]~55'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "0.258 ns" { lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51COUT1 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 8.058 ns lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[4\] 7 REG LAB_X14_Y7 4 " "Info: 7: + IC(0.000 ns) + CELL(0.898 ns) = 8.058 ns; Loc. = LAB_X14_Y7; Fanout = 4; REG Node = 'lpm_add_sub2:inst3\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[4\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "0.898 ns" { lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.199 ns ( 76.93 % ) " "Info: Total cell delay = 6.199 ns ( 76.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.859 ns ( 23.07 % ) " "Info: Total interconnect delay = 1.859 ns ( 23.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/ryu/桌面/新建文件夹/dds/" "" "8.058 ns" { bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a1~porta_address_reg0 bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43COUT1_67 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47COUT1_68 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51COUT1 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 3 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 3%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 30 13:12:42 2007 " "Info: Processing ended: Mon Jul 30 13:12:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}