dds.map.eqn

用FPGA实现DDS,可变频,幅值由硬件完成

--N17_sout_node[3] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]
--operation mode is arithmetic

N17_sout_node[3]_carry_eqn = N17L7;
N17_sout_node[3]_lut_out = N11L7 $ (N17_sout_node[3]_carry_eqn);
N17_sout_node[3] = DFFEAS(N17_sout_node[3]_lut_out, D1_clka, VCC, , , , , , );

--N17L9 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55
--operation mode is arithmetic

N17L9 = CARRY(!N17L7 # !N11L7);


--N17_sout_node[4] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]
--operation mode is arithmetic

N17_sout_node[4]_carry_eqn = N17L9;
N17_sout_node[4]_lut_out = N11L9 $ (!N17_sout_node[4]_carry_eqn);
N17_sout_node[4] = DFFEAS(N17_sout_node[4]_lut_out, D1_clka, VCC, , , , , , );

--N17L11 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~59
--operation mode is arithmetic

N17L11 = CARRY(N11L9 & (!N17L9));


--N17_sout_node[5] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]
--operation mode is normal

N17_sout_node[5]_carry_eqn = N17L11;
N17_sout_node[5]_lut_out = N11L11 $ (N17_sout_node[5]_carry_eqn);
N17_sout_node[5] = DFFEAS(N17_sout_node[5]_lut_out, D1_clka, VCC, , , , , , );


--D1L12 is fp:inst2|add~242
--operation mode is normal

D1L12_carry_eqn = D1L14;
D1L12 = D1_tout[7] $ (D1L12_carry_eqn);


--D1L13 is fp:inst2|add~247
--operation mode is arithmetic

D1L13_carry_eqn = D1L16;
D1L13 = D1_tout[6] $ (!D1L13_carry_eqn);

--D1L14 is fp:inst2|add~249
--operation mode is arithmetic

D1L14 = CARRY(D1_tout[6] & (!D1L16));


--D1L15 is fp:inst2|add~252
--operation mode is arithmetic

D1L15_carry_eqn = D1L18;
D1L15 = D1_tout[5] $ (D1L15_carry_eqn);

--D1L16 is fp:inst2|add~254
--operation mode is arithmetic

D1L16 = CARRY(!D1L18 # !D1_tout[5]);


--D1L17 is fp:inst2|add~257
--operation mode is arithmetic

D1L17_carry_eqn = D1L20;
D1L17 = D1_tout[4] $ (!D1L17_carry_eqn);

--D1L18 is fp:inst2|add~259
--operation mode is arithmetic

D1L18 = CARRY(D1_tout[4] & (!D1L20));


--D1L19 is fp:inst2|add~262
--operation mode is arithmetic

D1L19_carry_eqn = D1L24;
D1L19 = D1_tout[3] $ (D1L19_carry_eqn);

--D1L20 is fp:inst2|add~264
--operation mode is arithmetic

D1L20 = CARRY(!D1L24 # !D1_tout[3]);


--D1L21 is fp:inst2|add~267
--operation mode is arithmetic

D1L21_carry_eqn = D1L26;
D1L21 = D1_tout[1] $ (D1L21_carry_eqn);

--D1L22 is fp:inst2|add~269
--operation mode is arithmetic

D1L22 = CARRY(!D1L26 # !D1_tout[1]);


--D1L23 is fp:inst2|add~272
--operation mode is arithmetic

D1L23_carry_eqn = D1L22;
D1L23 = D1_tout[2] $ (!D1L23_carry_eqn);

--D1L24 is fp:inst2|add~274
--operation mode is arithmetic

D1L24 = CARRY(D1_tout[2] & (!D1L22));


--D1L25 is fp:inst2|add~277
--operation mode is arithmetic

D1L25 = !D1_tout[0];

--D1L26 is fp:inst2|add~279
--operation mode is arithmetic

D1L26 = CARRY(D1_tout[0]);


--H1_q_a[1] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[1]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[1]_PORT_A_address_reg = DFFE(H1_q_a[1]_PORT_A_address, H1_q_a[1]_clock_0, , , );
H1_q_a[1]_clock_0 = D1_clka;
H1_q_a[1]_PORT_A_data_out = MEMORY(, , H1_q_a[1]_PORT_A_address_reg, , , , , , H1_q_a[1]_clock_0, , , , , );
H1_q_a[1] = H1_q_a[1]_PORT_A_data_out[0];


--H1_q_a[0] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[0]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = D1_clka;
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0] = H1_q_a[0]_PORT_A_data_out[0];


--N32L8 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~69
--operation mode is normal

N32L8_carry_eqn = N32_cout[0];
N32L8 = N32L8_carry_eqn;


--clken is clken
--operation mode is input

clken = INPUT();


--clkin is clkin
--operation mode is input

clkin = INPUT();


--fr[0] is fr[0]
--operation mode is input

fr[0] = INPUT();


--fr[1] is fr[1]
--operation mode is input

fr[1] = INPUT();


--fr[2] is fr[2]
--operation mode is input

fr[2] = INPUT();


--fr[3] is fr[3]
--operation mode is input

fr[3] = INPUT();


--fr[4] is fr[4]
--operation mode is input

fr[4] = INPUT();


--fr[5] is fr[5]
--operation mode is input

fr[5] = INPUT();


--fr[6] is fr[6]
--operation mode is input

fr[6] = INPUT();


--fr[7] is fr[7]
--operation mode is input

fr[7] = INPUT();


--q7 is q7
--operation mode is output

q7 = OUTPUT(G1_q_a[7]);


--q6 is q6
--operation mode is output

q6 = OUTPUT(G1_q_a[6]);


--q5 is q5
--operation mode is output

q5 = OUTPUT(G1_q_a[5]);


--q4 is q4
--operation mode is output

q4 = OUTPUT(G1_q_a[4]);


--q3 is q3
--operation mode is output

q3 = OUTPUT(G1_q_a[3]);


--q2 is q2
--operation mode is output

q2 = OUTPUT(G1_q_a[2]);


--q1 is q1
--operation mode is output

q1 = OUTPUT(G1_q_a[1]);


--q0 is q0
--operation mode is output

q0 = OUTPUT(G1_q_a[0]);


--tt[7] is tt[7]
--operation mode is output

tt[7] = OUTPUT(G2_q_a[7]);


--tt[6] is tt[6]
--operation mode is output

tt[6] = OUTPUT(G2_q_a[6]);


--tt[5] is tt[5]
--operation mode is output

tt[5] = OUTPUT(G2_q_a[5]);


--tt[4] is tt[4]
--operation mode is output

tt[4] = OUTPUT(G2_q_a[4]);


--tt[3] is tt[3]
--operation mode is output

tt[3] = OUTPUT(G2_q_a[3]);


--tt[2] is tt[2]
--operation mode is output

tt[2] = OUTPUT(G2_q_a[2]);


--tt[1] is tt[1]
--operation mode is output

tt[1] = OUTPUT(G2_q_a[1]);


--tt[0] is tt[0]
--operation mode is output

tt[0] = OUTPUT(G2_q_a[0]);


--N32L5 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]~70
--operation mode is normal

N32L5 = !N32_sout_node[0];